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R5F10JBCAFP 数据表(PDF) 21 Page - Renesas Technology Corp |
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R5F10JBCAFP 数据表(HTML) 21 Page - Renesas Technology Corp |
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21 / 142 page ![]() RL78/G1C 2. ELECTRICAL SPECIFICATIONS (A: TA = -40 to +85°C) Page 21 of 138 R01DS0348EJ0140 Rev.1.40 Apr 26, 2024 2.2.3 PLL oscillator characteristics (TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V) Oscillators Parameters Conditions MIN. TYP. MAX. Unit PLL input frequency Note fPLLIN High-speed system clock 6.00 16.00 MHz PLL output frequency Note fPLL 48.00 MHz Lock up time From PLL output enable to stabilization of the output frequency 40.00 μ s Interval time From PLL stop to PLL re-operation setteing Wait time 4.00 μ s Setting wait time From after PLL input clock stabilization and PLL setting is fixed to start setting Wait time required 1.00 μ s Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. |
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