R5F10DMGLFB datasheet(80/139 Pages) RENESAS

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RL78/D1A

3. ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)

R01DS0463EJ0120 Rev. 1.20

Page 80 of 135

Mar 31, 2026

3.5.9 LCD Bus Interface characteristics (128-pin products only)

TA = -40 to +85

°C, 2.7 V ≤ EVDD0 = EVDD1 ≤ VDD ≤ 5.5 V, VSS = EVSS0 =EVSS1 =0 V

Items

Symbols

Conditions

MIN.

MAX.

Unit

Transfer frequency

MHz

CycleTime

tCYC

LBCYC x T

Control low pulse width

tCL

(LBWST + 1)T - 1

Enable active pulse width

tELH

(LBWST + 1)T - 5

Control setup time

tRWS

0.5TS - 8

Control hold time

tRWH

0.5T - 3

Data output setup time

tDOS

0.5TS - 6

0.5TS + 17

Data output hold time

tDOH

{LBCYC - (LBWST + 1.5)} T - 27

Data input setup time

tDIS

Data input hold time

tDIH

Output disable time

tOD

0.5T - 14

Remarks 1. T = (1/fCLK) × n (n: LCD Bus Interface clock n divider setting)

2. TS = (1/fCLK) × N (N: LCD Bus Interface no clock divider N = 1, n divider N = n - 1)

3. F = 1/tCYC

4. When EVDDx = SMVDDx

≤ VDD, LCD controller/driver related registers must be initial value (LCDON = 0,

SCOC = 0, MDSET1 – 0 = 00, LCDPFx = 0).

5. The above table shows the timing of LCD bus interface with Schmitt1 input characteristic.

Caution Different voltage between EVDD and VDD is allowed only when LCDM register is initial value.

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