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R5F10DMGLFB 数据表(PDF) 84 Page - Renesas Technology Corp

部件名 R5F10DMGLFB
功能描述  RENESAS MCU
PDF  139 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

R5F10DMGLFB 数据表(HTML) 84 Page - Renesas Technology Corp

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RL78/D1A
3. ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT)
R01DS0463EJ0120 Rev. 1.20
Page 84 of 135
Mar 31, 2026
TA = -40 to +85
°C, 2.7 V ≤ EVDD0 = EVDD1 = SMVDD0 = SMVDD1 = VDD ≤ 5.5 V, VSS = EVSS0 = EVSS1 = SMVSS0 = SMVSS1 = 0 V
Items
Symbols
Conditions
MIN.
TYP.
MAX.
Unit
LCD division
resistance Note 1
RLCD
3
k
Ω
LCD Segment output
voltage (unloaded)
VODS
IO =
±1 μA
VLCDn-0.05
VLCDn
Note 2
VLCDn+0.05
V
LCD Common output
voltage (unloaded)
VODC
IO =
±1 μA
VLCDn-0.05
VLCDn
VLCDn+0.05
V
LCD Segment
Output Voltage
(loaded)
VODSL0
IO =
±5 μA, all segment
pins at same time
VLCD0-0.6
VLCD0
VLCD0+0.6
V
VODSL1
IO =
±5 μA, all segment
pins at same time
VLCD1-0.6
VLCD1
VLCD1+0.6
V
VODSL2
IO =
±5 μA, all segment
pins at same time
VLCD2-0.6
VLCD2
VLCD2+0.6
V
VODSL3
IO =
±5 μA, all segment
pins at same time
VLCD3-0.6
VLCD3
VLCD3+0.6
V
LCD Common Output
Voltage (loaded)
VODCL0
IO =
±25 μA, single pin
VLCD0-0.2
VLCD0
VLCD0+0.2
V
VODCL1
IO =
±25 μA, single pin
VLCD1-0.2
VLCD1
VLCD1+0.2
V
VODCL2
IO =
±25 μA, single pin
VLCD2-0.2
VLCD2
VLCD2+0.2
V
VODCL3
IO =
±25 μA, single pin
VLCD3-0.2
VLCD3
VLCD3+0.2
V
LCD split voltage drive
capability
VLC0
IO = ±530
μA
VLCD0-0.1
VLCD0
VLCD0+0.1
V
VLC1
IO = ±530
μA
VLCD1-0.1
VLCD1
VLCD1+0.1
V
VLC2
IO = ±530
μA
VLCD2-0.1
VLCD2
VLCD2+0.1
V
VLC3
IO = ±530
μA
VLCD3-0.1
VLCD3
VLCD3+0.1
V
LCD output resistance
(COM) Note 3
RODC
10
k
Ω
LCD output resistance
(SEG) Note 3
RODS
10
k
Ω
Notes 1.
VLCDn (n= 0..3) represents one of the four possible voltage levels at the LCD pins. See table below for
reference.
VLCDn
no step-down transforming
VLCD0
VDD
VLCD1
2/3 VDD
VLCD2
1/3 VDD
VLCD3
VSS
2.
Only internal connection. The vaule is design specification.
3.
RODC is internal equivalent weight resistance from COM pin + COM IOBUF resistance.
RODS is internal equivalent weight resistance from SEG pin +SEG IOBUF resistance.



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