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R5F10DMGLFB 数据表(PDF) 16 Page - Renesas Technology Corp |
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R5F10DMGLFB 数据表(HTML) 16 Page - Renesas Technology Corp |
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16 / 139 page  RL78/D1A 1. OUTLINE R01DS0463EJ0120 Rev. 1.20 Page 16 of 135 Mar 31, 2026 1.6.3 64-pin products (R5F10CLD: with no CAN) TAU0 (8ch) TAU1 (8ch) TAU2 (8ch) SAU0 VLC0 to VLC2 (Note) COM0 to COM3 SEG0 to SEG9, SEG14 to SEG19, SEG21, SEG23 to SEG44 Note: No PAD LRxD0 LTxD0 SCL11 SDA11 SI01 SO01 SCK01 SI00 SO00 SCK00 TI27 TO27 TI25 TO25 TI23 TO23 TI22 TO22 TI21 TO21 TO21/TI20 TO20 RTC1HZ/TI17 TO17 RTC1HZ/TI16 TO16 TI15 TO15 TI14 TO14 TI13 TO13 TI12 TO12 TI11 TO11 TI10 TO10 RTC1HZ/TI07 TO07 RTC1HZ FSUB/FIL/TI05 TO05 TI03 TO03 TI01 TO01 TO01/TI00 TO00 LCD Controller / Driver UARTF0 SAU1 IIC11 CSI00 CSI01 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 ch 0 ch 1 ch 2 ch 3 ch 4 ch 5 ch 6 ch 7 Code Flash Data Flash RL78 CPU Core Clock Control & Reset Control POR/LVD Low Speed OCO 15 kHz Voltage Regulator PLL 4 MHz: x6, x8 8 MHz: x3, x4 Main OSC (2 to 20 MHz) RAM INT61 DMA 2 ch Multiplier & Divider, Multiply Accumulator BCD Adjustment OCD PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 PORT8 PORT9 PORT13 PORT12 PCL/BUZ Interrupt Control Window Watchdog Timer CRC RTC Interval timer 10 bit A/D Converter Stepper Motor Controller/ Driver Zero Point Detector Sound Generator REGC X1 X2/EXCLK RESET VDD, EVDD VSS, EVSS 7 P00 to P05, P07 7 P10 to P15, P17 5 P20 to P23, P27 4 P30 to P33 4 P54 to P57 P40 2 P60, P61 6 P70 to P75 8 P80 to P87 5 P90 to P94 4 P121 to P124 P137 PCL 6 INTP0 to INTP5 2 INTPLR0, 1 3 ANI2, ANI3, ANI7 ANI0/AVREF P ANI1/AVREF M ADTRG 2 ZPD14, ZPD24 SM11 to SM14 4 SMVDD SMVSS SGOA SGO/SGOF TI02 TO02 TI04 TO04 LRxD1 LTxD1 UARTF1 SubOSC 32.768 kHz XT1 XT2 SM21 to SM24 4 RTC1HZ <R> <R> |
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