R5F10DMGLFB datasheet(94/139 Pages) RENESAS

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RL78/D1A

4. ELECTRICAL SPECIFICATIONS (L GRADE PRODUCT)

R01DS0463EJ0120 Rev. 1.20

Page 94 of 135

Mar 31, 2026

TA = -40 to +105

°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V

Parameter

Symbols

Conditions

Typ.

Max.

Unit

Supply current,

halt mode

IDD2 Note 1

High speed

MAIN HALT

Note 3, 4, 5

fCLK = 24 MHz

fHOCO = 24 MHz

0.8

6.9

fHOCO = 4 MHz with PLL

fX = 4 MHz with PLL

fX = 8 MHz with PLL

fCLK = 20 MHz

fX = 20 MHz

0.7

6.0

fCLK = 8 MHz

fHOCO = 8 MHz

0.4

4.3

fX = 8 MHz

fCLK = 4 MHz

fHOCO = 4 MHz

0.35

3.6

fX = 4 MHz

SUB HALT

Note 3, 4, 6

fCLK = fXT

= 32.768 kHz

RTC is stopped

1.0

190

μA

RTC is operated by fXT

= 32.768 kHz

1.2

Supply current,

stop mode

IDD3 Note 2

STOP Note 3, 4

RTC and fXT are stopped

0.4

120

μA

RTC is operated by fXT = 32.768 kHz

0.8

Notes 1.

The common condition for IDD2:

- IDD includes the total current flowing into whole power pins, including the input leakage current flowing

when the level of the input pin is fixed to VDD or VSS.

- The HALT instruction is executed by the program in the code flash.

- The specification shows the stable current during HALT mode.

2. The common condition for IDD3:

- IDD includes the total current flowing into whole power pins, including the input leakage current flowing

when the level of the input pin is fixed to VDD or VSS.

- The STOP instruction is executed by the program in the code flash during MAIN RUN operation.

- The spec shows the stable current during STOP mode.

The typical value is that when TA = +25

°C and VDD = 5.0 V. Peripheral devices and the data flash are

stopped.

The maximum value is that when all peripheral devices are operating. But the A/D converter, LCD circuit,

stepper motor circuit, the data flash and the code flash are stopped. The 16-bit wakeup timer operates with

fLOCO.

5. Either fX or fHOCO which is selected for fCLK is operated. The other is stopped.

fX and fHOCO are stopped.

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