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RZ/A1H 数据表(PDF) 89 Page - Renesas Technology Corp |
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RZ/A1H 数据表(HTML) 89 Page - Renesas Technology Corp |
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89 / 137 page ![]() R01DS0479EJ0100 Rev.1.00 Page 89 of 137 Dec. 25, 2024 RZ/A1H Group, RZ/A1M Group 3. Electrical Characteristics Figure 3.32 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle) Notes: 1. An address pin to be connected to pin A10 of SDRAM. 2. The waveform for DACKn and TENDn is when active low is specified. Trc Trc Trc Trr Tpw Tp t CSD1 t AD1 t AD1 t RWD1 t RWD1 t RWD1 t CSD1 t CSD1 t CSD1 t RASD1 t RASD1 t RASD1 t RASD1 t AD1 t AD1 CKIO A25 to A0 CSn RD/ WR A12/A11 *1 D31 to D0 RAS t CASD1 t CASD1 CAS (Hi-Z) BS CKE DQMxx DACKn TENDn* 2 t CKED1 t CKED1 |
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