RZSLASHA1H datasheet(2/137 Pages) RENESAS

2 / 137 page

R01DS0479EJ0100 Rev.1.00

Page 2 of 137

Dec. 25, 2024

RZ/A1H Group, RZ/A1M Group

1. Overview

Overview

1.1

Outline of Specification

Table 1.1

Features of RZ/A1H and RZ/A1M

Items

Specification

CPU

 Arm Cortex-A9 processor

 Maximum operating frequency: 400 MHz

 Instruction cache size: 32 Kbytes

 Data cache size: 32 Kbytes (write-back algorithm)

 TLB entries: 128 entries

 Jazelle® architecture extension: Full implementation

 Media processing engine with NEONTM technology

L2 cache memory

 Arm CoreLink™ Level 2 Cache Controller L2C-310

 Operating frequency: 133 MHz

 Cache size: 128 Kbytes

Interrupt controller

 Arm PrimeCell® Generic Interrupt Controller (PL390)

 External interrupt pins (NMI, IRQ7 to IRQ0, and TINT170 to TINT0)

 On-chip peripheral interrupts: Priority level set for each module

 32 priority levels available

Bus state controller

 Address space divided into six areas (0 to 5), each a maximum of 64 Mbytes

 The following features settable for each area independently

—Bus size (8, 16, or 32 bits): Available sizes depend on the area.

—Number of access wait cycles (different wait cycles can be specified for read and write access

cycles in some areas)

—Idle wait cycle insertion (between the same area access cycles or different area access cycles)

—Specifying the memory to be connected to each area enables direct connection to SRAM, SRAM

with byte selection, SDRAM, and burst ROM (clocked synchronous or asynchronous). The

address/data multiplexed I/O (MPX) interface is also available.

 Outputs a chip select signal (CS0 to CS5) according to the target area (CS assert or negate timing

can be selected by software)

 SDRAM refresh

 Auto refresh or self refresh mode selectable

 SDRAM burst access

Direct memory access

controller

 Sixteen channels; external requests are available for one of them.

 Can be activated by on-chip peripheral modules.

 A specific DMA transfer interval can be specified to adjust the bus occupancy.

 Link mode (DMA transfer under descriptor control) supported

 Transfer information can be automatically reloaded.

Clock pulse generator

 Clock mode: Input clock can be selected from external input (EXTAL or USB_X1) or crystal

resonator.

 Input clock can be multiplied by 32 (max.) by the internal PLL circuit.

 Peak values of EMI noise can be reduced by the on-chip SSCG circuit.

 Five types of clocks generated:

—CPU clock (Iφ): Maximum 400.00 MHz

—Image processing clock (Gφ): Maximum 266.67 MHz

—Internal bus clock (Bφ): Maximum 133.33 MHz

—Peripheral clock 1 (P1φ): Maximum 66.67 MHz

—Peripheral clock 0 (P0φ): Maximum 33.33 MHz

Watchdog timer

 On-chip one-channel watchdog timer

 A counter overflow can reset the LSI.

Power-down modes

 Four power-down modes provided to reduce the power consumption in this LSI

—Sleep mode

—Software standby mode

—Deep standby mode

—Module standby mode

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