RZSLASHA1H datasheet(14/137 Pages) RENESAS

14 / 137 page

R01DS0479EJ0100 Rev.1.00

Page 14 of 137

Dec. 25, 2024

RZ/A1H Group, RZ/A1M Group

2. Pin

Operating mode

control

MD_BOOT2,

MD_BOOT1,

MD_BOOT0

Mode set

Sets the operating mode. Do not change

the signal levels on these pins while the

RES pin is asserted or until the mode is

fixed, after the negation.

MD_CLK

Clock mode set

Sets the clock operating mode. Do not

change the signal levels on this pin while

the RES pin is asserted or until the mode

is fixed, after the negation.

MD_CLKS

SSCG clock mode set

Switches the SSCG circuit on or off. Do

not change the signal levels on this pin

while the RES pin is asserted or until the

mode is fixed, after the negation.

BSCANP

Boundary scan set

Boundary scan setting pin.

This pin is set to the high level for a

boundary scan and to the low level for

normal operation.

System control

RES

Power-on reset

This LSI enters the power-on reset state

when this signal goes low.

WDTOVF

Watchdog timer

overflow

Outputs an overflow signal from the

watchdog timer.

Interrupts

NMI

Non-maskable

interrupt

Non-maskable interrupt request pin. It is

handled as an FIQ exception. Fix it high

when not in use.

IRQ7 to IRQ0

Interrupt requests 7 to

Maskable interrupt request pins.

Level-input or edge-input detection can

be selected. When the edge-input

detection is selected, the rising edge,

falling edge, or both edges can also be

selected.

TINT170 to TINT0

Interrupt requests 170

to 0

Maskable interrupt request pins.

Detection through input of the high level

or a rising edge can be selected.

Address bus

A25 to A0

Address bus

Outputs addresses.

Data bus

D31 to D0

I/O

Data bus

Bidirectional data bus.

Classification

Symbol

I/O

Name

Function

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