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STA015 数据表(PDF) 28 Page - STMicroelectronics

部件名 STA015
功能描述  MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY
PDF  55 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA015 数据表(HTML) 28 Page - STMicroelectronics

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DRB
Address: 0x49 (73)
Type: R/W
Software Reset: 0xFF
Hardware Reset: 0xFF
DRB register is used to re-direct the Right Channel on the Left, or to mix both the Channels. Default value
is 0x00, corresponding at the maximum attenuation in the re-direction channel.
CHIP_MODE
Address: 0x4D (77)
Type: R/W
Hardware Reset: 0x00
Using this register it’s possible to select which operation will be performed by the DSP.
Possible values are:
0x00 - MP3 decoding
0x01 - Reserved
0x02 - ADPCM Encoder
0x03 - ADPCM Decoder
0x04 - BYPASS mode
The DSP will check for the value of this register right after the RUN command has been issued (refer to
RUN register). After that no more checks will be performed: therefore a SOFT_RESET must be generated
in order to change the device mode.
CRCR
Address: 0x4E (78)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The CRC register is used to enable/disable the CRC check. If CRC_EN bit is cleared, the CRC value en-
coded in the bitstream is checked against the hardware one. If a discrepance occurs, the current frame is
skipped and the decoder is muted. The ERROR_CODE register is affected with the value 0x01.
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
Description
DRB7
DRB6
DRB5
DRB4
DRB3
DRB2
DRB1
DRB0
OUTPUT ATTENUATION
0
0
0
0
0
0
0
0
NO ATTENUATION
0
000
0
0
0
1
-1dB
0
000
0
0
1
0
-2dB
:
::::
:
:
:
:
0
110
0
0
0
0
-96dB
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
XX
XXXXX
CRCEN



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