STA015 datasheet(29/55 Pages) STMICROELECTRONICS

部件名	STA015

功能描述	MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY

PDF	55 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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STA015 STA015B STA015T

If CRC_EN bit is set, the result of the CRC check is ignored, but the ERROR_CODE register is neverthe-

less affected with the value 0x01 if a discrepance has occurred.

MFSDF_441

Address: 0x50 (80)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

This register contains the value for the PLL X driver for the 44.1KHz reference frequency.

The VCO output frequency, when decoding 44.1KHz bitstream, is divided by (MFSDF_441 +1)

PLLFRAC_441_L

Address: 0x51 (81)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

ADPCM_DATA_READY

Address: 0x52 (82)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

ADR: Adpcm Data Ready

This bit signal ADPCM encoded data are ready to be retrieved.

PLLFRAC_441_H

Address: 0x52 (82)

Type: R/W

Software Reset: 0x00

MSB

LSB

M4M3M2M1M0

MSB

LSB

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

MSB

LSB

XXXXX

ADR

STA015 数据表(PDF) 29 Page - STMicroelectronics

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