STA015 datasheet(33/55 Pages) STMICROELECTRONICS

33 / 55 page

33/55

STA015 STA015B STA015T

PCMCROSS

Address: 0x56 (86)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

The default configuration for this register is ’0x00’.

MFSDF (X)

Address: 0x61 (97)

Type: R/W

Software Reset: 0x07

Hardware Reset: 0x07

The register contains the values for PLL X divider (see Fig. 7).

The value is changed by the internal STA015 Core, to set the clocks frequencies, according to the incom-

ing bitstream. This value can be even set by the user to select the PCM interface configuration.

The VCO output frequency is divided by (X+1). This register is a reference for 32KHz and 48KHz input

bitstream.

DAC_CLK_MODE (99)

Address: 0x63

Type: RW

Software Reset: 0x00

Hardware Reset: 0x00

This register is used to select the operating mode for OCLK clock signal. If it is set to “1”, the OCLK fre-

quency is fixed, and it is mantained to the value fixed by the user even if the sampling frequency of the

incoming bitstream changes. It the MODE flag is set to f0f, the OCLK frequency changes, and can be set

to (512, 384, 256) * Fs. The default configuration for this mode is 256 * Fs. When this mode is selected,

MSB

LSB

Description

Left channel is mapped on the left output.

Right channel is mapped on the Right output

Left channel is duplicated on both Output channels.

Right channel is duplicated on both Output channels

Right and Left channels are toggled

MSB

LSB

M4M3M2M1M0

MSB

LSB

XXXXX

MODE

STA015 数据表(PDF) 33 Page - STMicroelectronics

STA015 数据表(HTML) 33 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

数据表下载