STA015 datasheet(32/55 Pages) STMICROELECTRONICS

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STA015 STA015B STA015T

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PCMCONF is used to set the PCM Output Interface configuration:

ORD: PCM order. If this bit is set to’1’, the LS Bit is transmitted first, otherwise MS Bit is transmiited first.

DIF: PCM_DIFF. It is used to select the position of the valid data into the transmitted word. This setting is

significant only in 18/20/24 bit/word mode.If it is set to ’0’ the word is right-padded, otherwise it is left-pad-

ded.

INV (fig.13): It is used to select the LRCKT clock polarity. If it is set to ’1’ the polarity is compliant to I2S

format (low -> left , high -> right), otherwise the LRCKT is inverted.

The default value is ’0’. (if I2S have to be selected, must be set to ’1’ in the TA013 configuration phase).

Figure 19. LRCKT Polarity Selection

FOR: FORMAT is used to select the PCM Output Interface format.

After hw and sw reset the value is set to 0 corresponding to I2S format.

SCL (fig.14): used to select the Transmitter Serial Clock polarity. If set to ’1’ the data are sent on the falling

edge and sampled on the rising. This last option is the most commonly used by the commercial DACs.

The default configuration for this flag is ’0’.

Figure 20. SCKT Polarity Selection

PREC [1:0]: PCM PRECISION

It is used to select the PCM samples precision, as follows:

’00’: 16 bit mode (16 slots transmitted)

’01’: 18 bit mode (32 slots transmitted)

’10’: 20 bit mode (32 slots transmitted)

’11’: 24 bit mode (32 slots transmitted)

The PCM samples precision in STA015 can be 16 or 18-20-24 bits.

When STA015 operates in 16 (18-20-24) bits mode, the number of bits transmitted during a LRCLT period

is 32 (64).

LEFT

LRCKT

INV_LRCLK=1

INV_LRCLK=0

LEFT

RIGHT

LEFT

D00AU1192

STA015 数据表(PDF) 32 Page - STMicroelectronics