STA015 datasheet(42/55 Pages) STMICROELECTRONICS

部件名	STA015

功能描述	MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY

PDF	55 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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STA015 STA015B STA015T

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ADC_CONF

Address: 0xBC (188)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

Using this register the ADC input interface can be configured as follow:

AIIS: ADC I2S mode

0 = sample word must be aligned with LRCK (no I2S mode)

1 = sample word not aligned with LRCK (I2S compliant mode)

ADC: ADC Data Config.

0 = sample word is LSB first

1 = sample word is MSB first

ASCP: ADC Serial Clock Polarity

0 = Data is sampled on rising edge

1 = Data is sampled an falling edge

ALRCP: ADC Left/Right Clock Polarity

ALRCS: ADC Left/Right Clock Start value. This two

bits permit to determine Left/Right clock

usage according to the following table:

MSB

LSB

ALRCS

ALRCP

ASCP

ADC

AIIS

ALRCP

ALRCS

LEFT/RIGHT COUPLE

(Data1, Data2)

(Data3, Data4)

(0, 1)

(2, 3)

(0, 1)

(2, 3)

(1, 2)

(3, 4)

DATA 0

LRCK

DATA

DATA 1

DATA 2

DATA 3

DATA 4

D99AU1065

STA015 数据表(PDF) 42 Page - STMicroelectronics

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