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SERCON816

3

ELECTRICAL (DC AND AC) CHARACTERISTICS

3.1 Absolute Maximum Ratings

WDOGN

24

O

Watchdog output (active low)

L_ERRN

32

O

Line error, active low: goes low when signal distortion is too high or when the

receive signal is missing. The operating mode is programmed by the

processor.

CYC_CLK

34

I

SERCOS interface cycle clock: CYC_CLK synchronizes the communication

cycles. The polarity is programmable.

CON_CLK

35

O

Control clock: becomes active within a communication cycle. Time, polarity

and width are programmable.

DIV_CLK

36

O

Divided control clock: becomes active several times within a communication

cycle or once in several communication cycles. Number of pulses, start time,

repetition rate and polarity are programmable, the pulse width is 1

µs.

SCLK

2

I

Serial clock for clock regeneration: the maximum frequency is 64 MHz.

SCLKO2

6

O

Clock output: outputs the SCLK clock divided by 2 or 1.

SCLKO4

5

O

Clock output: outputs the SCLK clock divided by 4 or 2.

MCLK

4

I

Master clock for telegram processing and timing control, frequency 12 to 64

MHz.

RSTN

10

I

Reset, active low. Must be zero for at least 50 ns after power on.

TEST

7

I

Test, active high. Has to be tied to VSS.

OUTZ

11

I

Puts outputs into high impedance state, active high: OUTZ is 1 puts all pins

into a high impedance state. The clocks are turned off and the circuit is reset.

For the in-circuit test and for turning on the power-down mode.

NDTRO

9

O

NAND tree output. For the test at the semiconductor manufacturers and for

the connection test after board production. NDTRO is not set to a high

impedance state.

VSS

3,15,23,33

,42,50,60,

70,81,91

Ground pins:

VDD

1,8,19,27,

37,55,65,

76,86

Power supply +5 V ± 5%.

Symbol

Parameter

Value

Unit

Supply voltage

-0.5 to 6.5

V

Input voltage

V

Output voltage

V

Storage temperature

-55 to +150

°C

Table 1. SERCON816 I/O Port Function Summary (continued)

Signal(s)

Pin(s)

IO

Function