9/23

SERCON816

Notes: 1. estimated

3.4.1 Power Dissipation Considerations

Most of the current consumed by CMOS devices is alternate current (AC) which is charging and discharg-

ing the capacitances of the pins and internal nodes. The current consumption rises with the frequency at

which the pins and internal nodes will toggle and with the capacitances connected to the pins of the device:

For applications which require low power consumption or exceeds the maximum allowed power consump-

tion the following is required:

– Connect unused pins to pull-up or pull-down resistors

– Minimize the capacitive load on the pins

– Reduce clock frequency of SCLK and MCLK

– Minimize accesses to the internal RAM and control registers

The maximum allowed power consumption is limited by the maximum allowed chip junction temperature

and by the number of VCC/VDD pins. The chip junction temperature is influenced by the ambient temper-

ature and the package thermal resistance. The ambient temperature could be influenced by the applica-

tion through a good temperature management like heat sinks or ambient air cooling.

Low level output voltage, pins

TXD6-1, L_ERRN

0.4

V

High level output voltage, pins

TXD6-1, L_ERRN

2.4

Tri-state output leakage

1

µA

I/O latch-up current

200

mA

Electrostatic protection

Leakage < 1 µA, human body

model

2000

V

Pin capacitance

10

pF

3.4 Power Dissipation

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

Power dissipation

16 Mbaud, MCLK=64 MHz

mW

Maximum allowed power

dissipation

1000

mW

3.3 ELECTRICAL CHARACTERISTCS (continued)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit