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SERCON816 数据表(PDF) 13 Page - STMicroelectronics |
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SERCON816 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 23 page ![]() 13/23 SERCON816 3.5.5 Read Access of Dual Port RAM Figure 9. Read Access of Dual Port RAM Notes: 1. Setup time input signals to falling edge RDN (Intel or Motorola mode with low active strobe) or rising edge RDN (Motorola mode with high active strobe) Symbol Parameter Min. Typ. Max. Unit tASU Setup time A11-0, (Note 1) 10 ns Setup time MCSN0-1, if both signals are activated simultaneously. (Note 1) 5ns Setup time MCSN0-1, if one of these both signals is activated 10 ns earlier. (Note 1) 0ns Setup time BHEN, WRN (only Motorola mode), (Note 1) 0 ns tAHD hold time A11-0, BHEN, MCSN0-1, WRN (only Motorola mode) to rising edge RDN (Intel Motorola mode with low active strobe) or falling edge RDN (Motorola mode with high active strobe) 0ns tRDNCLK Cycle time of RAM read clock SBAUD16 = 1 (fRDNCLK = fSCLK) 1 / fSCLK SBAUD16 = 0 (fRDNCLK = 2 * fSCLK) 0.5 / fSCLK tMRDD access time RDN to D15-0 valid 2 * tRDNCLK + 30 ns tMBSY delay RDN to BUSYN low 15 ns tMBHD Delay BUSYN high to D15-0 valid 2 * tRDNCLK + 30 ns tRDZ Delay RDN to D15-0 high-Z 20 ns tRD1 RDN and WRN high after end of read access 15 ns A10-0, BHEN, MCSN0-1, WRN (Motorola mode) RDN D15-0 BUSYN tMBSY tMBHD tRDZ tRD1 tMRDD tASU tAHD |
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