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TDA7590 数据表(PDF) 21 Page - STMicroelectronics |
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TDA7590 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 40 page  TDA7590 Appendix 1 21/40 IPR_P EQU $FFFFFE ; Interrupt Priority Register Peripheral ; SAI interrupt Vectors SAI_ROF EQU $070 ; Receiver Overflow SAI_TUF EQU $072 ; Transmitter Underflow SAI_RDR EQU $074 ; Receiver Data Ready SAI_TDE EQU $076 ; Transmitter Data Empty ; Timer interrupt Vector Timer0_tcf equ $24 ; Timer0 Compare Timer0_tof equ $26 ; Timer0 Overflow Timer1_tcf equ $28 ; Timer1 Compare Timer1_tof equ $2A ; Timer1 Overflow Timer2_tcf equ $2C ; Timer2 Compare Timer2_tof equ $2E ; Timer2 Overflow ; SCI Interrupt Vectors SCI_REC EQU $000050 ; SCI receive data SCI_REC_E EQU $000052 ; SCI receive data with exception status SCI_TRANS EQU $000054 ; SCI transmit data SCI_IDLE EQU $000056 ; SCI idle line SCI_TIMER EQU $000058 ; SCI timer ;;; Bit Definition for SCI_SSR FRAMING EQU 6 RESET EQU $000000 ; Reset address location ;------------------------------------------------------------------------ ; EQUATES for SAI (y memory) ;------------------------------------------------------------------------ SAI_RCS EQU $FFFFFF ; SAI Receive Control/Status Register SAI_RX2 EQU $FFFFFE ; SAI Channel 2 Receiver Data SAI_RX1 EQU $FFFFFD ; SAI Channel 1 Receiver Data SAI_RX0 EQU $FFFFFC ; SAI Channel 0 Receiver Data SAI_TCS EQU $FFFFFB ; SAI Transmit Control/Status Register SAI_TX2 EQU $FFFFFA ; SAI Channel 2 Transmitter Data SAI_TX1 EQU $FFFFF9 ; SAI Channel 1 Transmitter Data SAI_TX0 EQU $FFFFF8 ; SAI Channel 0 Transmitter Data ;;; Bit Definitions for M_RCS ROFCL EQU 16 ; Receiver Data Overflow Clear RDR EQU 15 ; Receiver Data Ready ROFL EQU 14 ; Receiver Data Overflow ;Reserved RXIE EQU 12 ; Receiver Interrupt Enable RDWJ EQU 11 ; Receiver Data Word Justification RREL EQU 10 ; Receiver Relative Timing RCKP EQU 9 ; Receiver Clock Polarity RLRS EQU 8 ; Receiver Left Right Selection RDIR EQU 7 ; Receiver Data Shift Direction RWL1 EQU 6 ; Receiver Word Length Control 1 RWL0 EQU 5 ; Receiver Word Length Control 0 ;Reserved RMME EQU 3 ; Receiver Master Mode Enable R2EN EQU 2 ; Receiver 2 enable R1EN EQU 1 ; Receiver 1 enable R0EN EQU 0 ; Receiver 0 enable |
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