Appendix 1

TDA7590

32/40

movep

#INIT_PLL_FCR,x:PLL_FCR

; set fract value.

bset

#FRACEN,x:<<PLL_CSR

; enable fractional-n operation.

movep

#INIT_PLL_CLKCTL,x:PLL_CLKCTL

; setup the clock generation.

IF 1

;------------------------------------------------------------------------

;

Initialise CODEC

;------------------------------------------------------------------------

init_codec

movep

#INIT_CODEC_CSR,x:CODEC_CSR

; initialise CODEC control/status reg

;------------------------------------------------------------------------

;

Initialise SAI

;------------------------------------------------------------------------

; The receiver and transmitter control/status register are configured the same for simplicity only.

; Master mode , 24-bit word-size , MSB first , Low word clock = left word , Neg bit-clk polarity ,

; Non i2s format ,

(For 32-bit words) First bit x 8 , Interrupts enabled.

init_sai

movep

#INIT_SAI_TCS,y:SAI_TCS

; initialise transmit control/status reg

movep

#INIT_SAI_RCS,y:SAI_RCS

; initialise receiver control/status reg

;------------------------------------------------------------------------

; Enable gpios for HI

;------------------------------------------------------------------------

bset

#GPIO0_DIR,x:GPIOCTRL

; Setup HI pin for GPIO mode

bset

#GPIO0_DIR,x:GPIODIR

; Setup GPIO as output

bset

#GPIO1_DIR,x:GPIOCTRL

; Setup HI pin for GPIO mode

bset

#GPIO1_DIR,x:GPIODIR

; Setup GPIO as output

ENDIF

;------------------------------------------------------------------------

; Initialize ESSI0

;------------------------------------------------------------------------

IF 1

init_essi

movep #$181801,x:M_CRA0 ; cra0_addr, 24'b010110000001100000011110

; The divider control is set to 1 (2 words per frame)

; for Normal mode, bits are left aligned to bit 23.

Word

; length is set to 24 bits.PM = 1 -> Fcore/4.

movep #$fc113e,x:M_CRB0 ; crb0_addr, 24'b111111000001010100111110

; The receive exception and transmit exception interrupts

; are enabled as are receive last slot and transmit last

; slot. It is set in the synchronous normal mode. Data and

; frame sync are clocked out on the rising edge of the clock.

; Frame sync polarity is positive and occurs together with the

; the first bit of data from the first slot.

MSB is shifted

; first. SC2 o/p SC1 o/p SC0 o/p

Enable_pins

;------------------------------------------------------------------------

move

#$01c000,x0

;

movep x:M_CRB0,b1

;

or

x0,b1

;

// Enable TX2/TX1/TX0 (ESSI 0)

movep #$00003f,x:M_PCRC ; // ALL Pins are ESSI.

; check that all pins are enabled

rep

#$05

nop