ST6391 datasheet(13/68 Pages) STMICROELECTRONICS

13 / 68 page

ST639x CORE (Continued)

Stack

The ST639x Core includes true LIFO hardware

stack that eliminates the need for a stack pointer.

The stack consists of six separate 12-bit RAM lo-

cations that do not belong to the data space RAM

area. When a subroutine call (or interrupt request)

occurs, the contents of each level is shifted into the

next level while the content of the PC is shifted into

the first level (the value of the sixth level will be

lost). When subroutine or interrupt return occurs

(RET or RETI instructions), the first level register is

shifted back into the PC and the value of each level

is shifted back into the previous level. These two

operating modes are described in Figure 7. Since

the accumulator, as all other data space registers,

is not stored in this stack the handling of this regis-

ters shall be performed inside the subroutine. The

stack pointer will remain in its deepest position, if

more than 6 calls or interrupts are executed, so

that the last return address will be lost. It will also

remain in its highest position if the stack is empty

and a RET or RETI is executed. In this case the

next instruction will be executed.

Memory Registers

The PRPR can be addressed like a RAM location

in the Data Space at the CAh address; neverthe-

less it is a write-only register that can not be ac-

cessed with single-bit operations. This register is

used to select the 2-Kbyte ROM bank of the Pro-

gram Space that will be addressed. The number of

the page has to be loaded in the PRPR. The PRPR

is not cleared during the MCU initialization and

should therefore be defined before jumping out of

the static page. Refer to the Program Space de-

scription for additional information concerning the

use of this register. The PRPR is not modified

when an interrupt or a subroutine occurs.

PRPR

Program ROM Page Register

(CAh, Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

Figure 8. Program ROM Page Register

DRBR

Data RAM Bank Register

(E8h, Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

Figure 9. Data RAM Bank Register

DRWR

Data ROM Window Register

(C9h, Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

Figure 10. Data ROM Window Register

The DRBR can be addressed like a RAM location

in the Data Space at the E8h address, neverthe-

less it is write-only register that can not be ac-

cessed with single-bit operations. This register is

used to select the desired 64-byte RAM/EEPROM

bank of the Data Space. The number of the bank

has to be loaded in the DRBR and the instruction

has to point to the selected location as it was in the

0 bank (from 00h address to 3Fh address). This

Space description for additional information. The

DRBR register is not modified when a interrupt or a

subroutine occurs.

The DRWR register can be addressedlike a RAM lo-

cation in the Data Space at the C9h address, never-

theless it is write-only register that can not be

accessed with single-bit operations. This register is

used to move up and down the 64-byte read-only

data window (from the 40h address to 7Fh address

of the Data Space) along the ROM of the MCU by

step of 64 bytes. The effective address of the byte to

be read as a data in the ROM is obtainedby the con-

catenationof the 6 less significant bits of the address

given in the instruction (as less significant bits) and

the content of the DRWR (as most significant bits).

Refer to the Data Space description for additional in-

formation.

ST6391,92,93,95,97,99

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