ST6391 datasheet(37/68 Pages) STMICROELECTRONICS

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D7-D4. These bits are not used.

STR. This is Start bit for I

2CBUS/S-BUS. This bit is

meaningless when STD/SPI enable bit is cleared to

zero. If this bit is set to one STD/SPI bit is also set to

“1” and SPI Start generation, before beginning of

transmission, is enabled. Set to zero after reset.

STP. This is Stop bit for I

2CBUS/S-BUS. This bit is

meaningless when STD/SPI enable bit is cleared

to zero. If this bit is set to one STD/SPI bit is also

set to “1” and SPI Stop condition generation is en-

abled. STP bit must be reset when standard proto-

col is used (this is also the default reset

conditions). Set to zero after reset.

STD, SPI Enable. This bit, in conjunction with S-

BUS/I

2CBUS bit, allows the SPI disable and will

select between I

2CBUS/S-BUS and Standard

shift register protocols. If this bit is set to one, it

selects both I

2CBUS and S-BUS protocols; final

selection

between

them

made

S-

BUS/I

2CBUS bit. Ifthis bit is cleared to zero when

S-BUS/I

2CBUS is set to “1” the Standard shift

to “0” when S-BUS/I

2CBUS is cleared to 0 the SPI

is disabled. Set to zero after reset.

S-BUS/I

2CBUS Selection. This bit, in conjunction

with STD/SPI bit, allows the SPI disable and will

select between I

2CBUS and S-BUS protocols. If

this bit is cleared to “0” when STD bit is also “0”, the

SPI interface is disabled. If this bit is cleared to zero

when STD bit is set to “1”, the I

2CBUS protocol will

be selected. If this bit is set to “1” when STD bit is

set to “1”, the S-BUS protocol will be selected.

Cleared to zero after reset.

SCR1

SPI Control Register 1

(EBh, Write only)

D7 D6 D5 D4 D3 D2 D1 D0

S-BUS/I

C BUS Selection

STD/SPI Enable

STP = Stop Bit

STR = Start Bit

Unused

Figure 41. SPI Control Register 1

SERIAL PERIPHERAL INTERFACE (Continued)

D7-D4. These bits are not used.

TX/RX.Write Only. When this bit is set, current byte

operation is a transmission. When it is reset, cur-

rent operation is a reception. Set to zero after re-

set.

VRY/S.Read Only/Write Only. This bit has two dif-

ferent functions in relation to read or write opera-

tion. Reading Operation: when STD and/or TRX

bits is cleared to 0, this bit is meaningless. When

bits STD and TX are set to 1, this bit is set each

time BSY bit is set. This bit is reset during byte op-

eration if real data on SDA line are different from

the output from the shift register. Set to zero after

reset. Writing Operation : it enables (if set to one)

or disables (if cleared to zero) the interrupt coming

from VSYNC pin. Undefined after reset. Refer to

OSD description for additional information.

ACN.Read Only. If STD bit (D1 of SCR1 register) is

cleared to zero this bit is meaningless. When STD

is set to one, this bit is set to one if no Acknowledge

has been received. In this case it is automatically

reset when BSY is set again. Set to zero after re-

set.

BSY.Read/Set Only. This is the busy bit. When a

one is loaded into this bit the SPI interface start the

transmission of the data byte loaded into SSDR

data register or receiving and building the receive

data into the SSDR data register. This is done in

accordance with the protocol, direction and

start/stop condition(s). This bit is automatically

cleared at the end of the current byte operation.

Cleared to zero after reset.

Note :

The SPI shift register is also the data transmission

is made possible by using the serial structure of the

ST639x and thus reducing size and complexity.

STD/SP

S-BUS/I

2C BUS

SPI Function

Disabled

STD Shift Reg.

2C BUS

S-BUS

Table 10. SPI Modes Selection

SCR2

SPI Control Register 2

(ECh, Read/ Write)

D7 D6 D5 D4 D3 D2 D1 D0

BSY = Busy Bit 0

ACN = Acknowledge Bit

VRY/S = Verify/Sync.Enab le

TX/RX = Enable Bit

Unuse d

Figure 42. SPI Control Register2

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