ST6391 datasheet(45/68 Pages) STMICROELECTRONICS

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6-BIT PWM D/A CONVERTERS

The D/A macrocell contains up to six PWM D/A

outputs (31.25kHz repetition, DA0-DA5) with six bit

resolution.

Each D/A converter of ST639x is composed by the

following main blocks:

- pre-divider

- 6-bit counter

- data latches and compare circuits

The pre-divider uses the clock input frequency

(8MHz typical) and its output clocks the 6-bit free-

running counter. The data latched in the six regis-

ters (E0h, E1h, E2h, E3h, E6h and E7h) control the

six D/A outputs (DA0,1,2, 3, 4 and 5). When all ze-

ros are loaded the relevant output is an high logic

level; all 1’s correspond to a pulse with a 1/64 duty

cycle and almost 100% zero level.

The repetition frequency is 31.25kHz and is related

to the 8MHz clock frequency. Use of a different os-

cillator frequency will result in a different repetition

frequency. All D/A outputs are open-drain with

standard current drive capability and able to with-

stand up to 12V.

DA0-DA5. These are the 6 bits of the PWM digital

to analog converter. Undefined after reset.

AFC A/D COMPARATOR

AFC A/D INPUT,IR/PC6 RESULT, VSYNC RESULT

The AFC macrocell contains an A/D comparator

with five levels at intervals of 1V from 1V to 5V. The

levels can all be lowered by 0.5V to effectively dou-

ble the resolution.

A/D Comparator

The A/D used to perform the AFC function (when

high threshold is selected) has the following volt-

age levels: 1,2,3,4 and 5V. Bits 0-2 of AFC result

nary form (less than 1V is 000, greater than 5V is

101).

If the application requires a greater resolution, the

sensitivity can be doubled by clearing to zero bit 2

of the OUTPUTS control register, address E5h. In

this case all levels are shifted lower by 0.5V. If the

two results are now added within a software rou-

tine then the A/D S-curve can be located within a

resolution of 0.5V.

The A/D input has high impedance able to with-

stand up to 13V signals (input level tolerances

±200mV absolute and ± 100mv relative to 5V).

DA0, DA1, DA2, DA3, DA4, DA5

DA0 to DA5 Data/control Registers

(E0h, E1h, E2h, E3h, E6h, E7h Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

Data Bit 0

Data Bit 1

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Unused

Figure 50. DA0-DA5 Data/Control Registers

Figure 51.6-bit PWM D/A Output Configuration

Figure 52. AFC Inputs Configuration Diagram

ST6391,92,93,95,97,99

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