ST6391 datasheet(51/68 Pages) STMICROELECTRONICS

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D7. This bit is not used

FR. Fringe Background.This bit changes the back-

ground from a box background to a fringe back-

ground. The background is enabled by word as

defined by either BG0 or BG1.

“0” -The background is defined to be a box which is

7 x 9 dots.

“1” -The background is defined to be a fringe.

VSA5-VSA0. Vertical Start Address. These bits

determine the start position of the first line in the

vertical direction. The 6 bits can specify 63 display

start positions of interval 4H. The first start position

will be the fourth line of the display. The vertical

start address is defined VSA0 by the following for-

mula.

Vertical Start Address = 4H(2

5(VSA5) + 24(VSA4)

3(VSA3) + 22(VSA2) + 21(VSA1) + 20(VSA0))

The case of all Vertical Start Address bits being

zero is illegal.

D7. This bit is not used.

SBD. Space Blanking Disable. This bit controls

whether or not the background is displayed when

outputting spaces. If two background colours are

used on adjacent words, then the background

should not be displayed on spaces in order to

make a nice break between colours. If an even

background around an area of text is desired, as in

a menu, then the background should be displayed

when outputting spaces.

“0” -The background during spaces is controlled by

the background enable bits (BG0 and BG1) lo-

cated in the Background Control register.

“1” -The background is not displayed when output-

ting spaces.

HSA5, HSA0 - Horizontal Start Address bits.

These bits determine the start position of the first

character in the horizontal direction. The 6 bits can

specify 64 display start positions of interval 2/fosc or

400ns. The first start position will be at 4.0

µs be-

cause of the time need ed to access RAM and

ROM before the first character can be displayed.

The horizontal start address is defined by the fol-

lowing formula.

Horizontal Start Address = 2/fosc(10.0 + 2

5(HSA5)

4(HSA4) + 23(HSA3) + 22(HSA2) + 21(HSA1) +

0(HSA0))

ON-SCREEN DISPLAY (Continued)

VSAR

Vertical Start Address Register

(10h - Page 6, Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

VSA5-VSA0 = Vertical Start

Address bits

FR = Fringe Backround

Control bit

Unused

Figure 60. Vertical Start Address Register

HSAR

Horizontal Start Address Register

(11h - Page 6, Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

HSA5-HSA0 = Horizontal Start

Address bits

SBD = Space Blanking

Disabled bit

Unuse d

Figure 61. Horizontal Start Address Register

ST6391,92,93,95,97,99

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