ST6391 datasheet(56/68 Pages) STMICROELECTRONICS

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SOFTWARE DESCRIPTION

The ST63xx software has been designed to fully

use the hardware in the most efficient way possible

while keeping byte usage to a minimum; in short to

provide byte efficient programming capability. The

ST63xx Core has the ability to set or clear any

a single instruction. Furthermore, the program may

branch to a selected address depending on the

status of any bit of the Data space. The carry bit is

stored with the value of the bit when the SET or

RES instruction is processed.

Addressing Modes

The ST63xx Core has nine addressing modes

which are described in the following paragraphs.

The ST63xx Core uses three different address

spaces : Program space, Data space, and Stack

space. Program space contains the instructions

which are to be executed, plus the data for imme-

diate mode instructions. Data space contains the

Accumulator, the X,Y,V and W registers, peripheral

and Input/Outputregisters, the RAM locations and

Data ROM locations (for storage of tables and

constants). Stack space contains six 12-bit RAM

cells used to stack the return addresses for subrou-

tines and interrupts.

Immediate. In the immediate addressing mode,

the operand of the instruction follows the opcode

location. As the operand is a ROM byte, the imme-

diate addressing mode is used to access constants

which do not change during program execution

(e.g., a constant used to initialize a loop counter).

Direct. In the direct addressing mode, the address

of the byte that is processed by the instruction is

stored in the location that follows the opcode. Direct

addressing allows the user to directly address the

256 bytes in Data Space memory with a single

two-byte instruction.

Short Direct. The Core can address the four RAM

registers X,Y,V,W (locations 80H, 81H, 82H, 83H)

in the short-direct addressing mode. In this case,

the instruction is only one byte and the selection of

the location to be processed is contained in the

opcode. Short direct addressing is a subset of the

direct addressing mode. (Note that 80H and 81H

are also indirect registers).

Extended. In the extended addressing mode, the

12-bit address needed to define the instruction is

obtained by concatenating the four less significant

bits of the opcode with the byte following the op-

code. The instructions (JP, CALL) that use the

extended addressing mode are able to branch to

any address of the 4K bytes Program space.

An extended addressing mode instruction is two-

byte long.

Program Counter Relative. The relative address-

ing mode is only used in conditional branch instruc-

tions. The instruction is used to perform a test and,

if the condition is true, a branch with a span of -15

to +16 locations around the address of the relative

instruction. If the condition is not true, the instruc-

tion that follows the relative instruction is executed.

The relative addressing mode instruction is one-

byte long. The opcode is obtained in adding the

three most significant bits that characterize the kind

of the test, one bit that determines whether the

branch is a forward (when it is 0) or backward (when

it is 1) branch and the four less significant bits that

give the span of the branch (0h to Fh) that must be

added or subtracted to the address of the relative

instruction to obtain the address of the branch.

Bit Direct. In the bit direct addressing mode, the

bit to be set or cleared is part of the opcode, and

the byte following the opcode points to the address

of the byte in which the specified bit must be set or

cleared. Thus, any bit in the 256 locations of Data

space memory can be set or cleared.

Bit Test & Branch. The bit test and branch ad-

dressing mode is a combination of direct address-

ing and relative addressing. The bit test and branch

instruction is three-byte long. The bit identification

and the tested condition are included in the opcode

byte. The address of the byte to be tested follows

immediately the opcode in the Program space. The

third byte is the jump displacement, which is in the

range of -126 to +129. This displacement can be

determined using a label, which is converted by the

assembler.

Indirect. In the indirect addressing mode, the byte

processed by the register-indirect instruction is at

the address pointed by the content of one of the

indirect registers, X or Y (80H,81H). The indirect

Inherent. In the inherent addressing mode, all the

information necessary to execute the instruction is

contained in the opcode. These instructions are

one byte long.

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