ST7262 datasheet(90/132 Pages) STMICROELECTRONICS

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ST7262

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10-BIT A/D CONVERTER (ADC) (Cont’d)

To read only 8 bits, perform the following steps:

1. Wait for interrupt or poll the EOC bit

2. Read ADCDRMSB

The EOC bit is reset by hardware once the AD-

CDRMSB is read.

To start another conversion, user should set the

ADON bit once again.

ADC Continuous Conversion mode

In the ADCCSR register:

1.Reset the ONE SHOT bit to put the A/D con-

verter in continuous mode.

2.Set the ADON bit to enable the A/D converter

and to start the first conversion. From this time

on, the ADC performs a continuous conversion

of the selected channel.

Note: Changing the A/D channel during conver-

sion will stop the current conversion and start con-

version of the newly selected channel.

When a conversion is complete:

– The EOC bit is set by hardware.

– An interrupt request is generated if the ITE bit

is set.

– The result is in the ADCDR registers and re-

mains valid until the next conversion has end-

ed.

To read the 10 bits, perform the following steps:

1. Wait for interrupt or poll the EOC bit

2. Read ADCDRLSB

3. Read ADCDRMSB

The EOC bit is reset by hardware once the AD-

CDRMSB is read.

To read only 8 bits, perform the following steps:

1. Wait for interrupt

2. Read ADCDRMSB

The EOC bit is reset by hardware once the AD-

CDRMSB is read.

Changing the conversion channel

The application can change channels during con-

version. In this case the current conversion is

stopped and the A/D converter starts converting

the newly selected channel.

ADCCR consistency

If an End Of Conversion event occurs after soft-

ware has read the ADCDRLSB but before it has

read the ADCDRMSB, there would be a risk that

the two values read would belong to different sam-

ples.

To guarantee consistency:

– The ADCDRMSB and the ADCDRLSB are

locked when the ADCCRLSB is read

– The ADCDRMSB and the ADCDRLSB are un-

locked when the MSB is read or when ADON

is reset.

Thus, it is mandatory to read the ADCDRMSB just

after reading the ADCDRLSB. This is especially

important in continuous mode, as the ADCDR reg-

ister will not be updated until the ADCDRMSB is

read.

10.7.4 Low Power Modes

Note: The A/D converter may be disabled by re-

setting the ADON bit. This feature allows reduced

power consumption when no conversion is need-

ed and between single shot conversions.

10.7.5 Interrupts

Note: The EOC interrupt event is connected to an

interrupt vector (see Interrupts chapter).

It generates an interrupt if the ITE bit is set in the

ADCCSR register and the interrupt mask in the CC

Mode

Description

WAIT

No effect on A/D Converter

HALT

A/D Converter disabled.

After wakeup from Halt mode, the A/D

Converter requires a stabilisation time

tSTAB (see Electrical Characteristics)

before accurate conversions can be

performed.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

End of Conversion

EOC

ITE

Yes

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