ST7262 datasheet(53/132 Pages) STMICROELECTRONICS

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ST7262

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TIMEBASE UNIT (Cont’d)

10.3.5 Low Power Modes

10.3.6 Interrupts

Note: The OVF interrupt event is connected to an

interrupt vector (see Interrupts chapter).

It generates an interrupt if the ITE bit is set in the

TBUCSR register and the I-bit in the CC register is

reset (RIM instruction).

10.3.7 Register Description

TBU COUNTER VALUE REGISTER (TBUCV)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:0 = CV[7:0]

Counter Value

This register contains the 8-bit counter value

which can be read and written anytime by soft-

ware. It is continuously incremented by hardware if

TCEN=1.

TBU CONTROL/STATUS REGISTER (TBUCSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = Reserved. Forced by hardware to 0

Bit 6 = CAS

Cascading Enable

This bit is set and cleared by software. It is used to

cascade the TBU and the PWM/ART timers.

0: Cascading disabled

1: Cascading enabled

Bit 5 = OVF

Overflow Flag

This bit is set only by hardware, when the counter

value rolls over from FFh to 00h. It is cleared by

software reading the TBUCSR register. Writing to

this bit does not change the bit value.

0: No overflow

1: Counter overflow

Bit 4 = ITE

Interrupt enabled.

This bit is set and cleared by software.

0: Overflow interrupt disabled

1: Overflow interrupt enabled. An interrupt request

is generated when OVF=1.

Bit 3 = TCEN

TBU Enable.

This bit is set and cleared by software.

0: TBU counter is frozen and the prescaler is reset.

1: TBU counter and prescaler running.

Bit 2:0 = PR[2:0]

Prescaler Selection

These bits are set and cleared by software to se-

lect the prescaling factor.

Mode

Description

WAIT

No effect on TBU

HALT

TBU halted.

Interrupt

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Counter Over-

flow Event

OVF

ITE

Yes

CV7

CV6

CV5

CV4

CV3

CV2

CV1

CV0

CAS OVF

ITE

TCEN

PR2

PR1

PR0

PR2

PR1

PR0

Prescaler Division Factor

000

001

010

011

100

101

110

128

111

256

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