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ST7262 数据表(PDF) 47 Page - STMicroelectronics |
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ST7262 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 132 page ![]() ST7262 47/132 PWM AUTO-RELOAD TIMER (Cont’d) Input capture function This mode allows the measurement of external signal pulse widths through ICRx registers. Each input capture can generate an interrupt inde- pendently on a selected input signal transition. This event is flagged by a set of the corresponding CFx bits of the Input Capture Control/Status regis- ter (ICCSR). These input capture interrupts are enabled through the CIEx bits of the ICCSR register. The active transition (falling or rising edge) is soft- ware programmable through the CSx bits of the ICCSR register. The read only input capture registers (ICRx) are used to latch the auto-reload counter value when a transition is detected on the ARTICx pin (CFx bit set in ICCSR register). After fetching the interrupt vector, the CFx flags can be read to identify the in- terrupt source. Note: After a capture detection, data transfer in the ICRx register is inhibited until the ARTICCSR register is read (clearing the CFx bit). The timer interrupt remains pending while the CFx flag is set when the interrupt is enabled (CIEx bit set). This means, the ARTICCSR register has to be read at each capture event to clear the CFx flag. The timing resolution is given by auto-reload coun- ter cycle time (1/fCOUNTER). During HALT mode, input capture is inhibited (the ICRx is never re-loaded) and only the external in- terrupt capability can be used. External interrupt capability This mode allows the Input capture capabilities to be used as external interrupt sources. The edge sensitivity of the external interrupts is programmable (CSx bit of ICCSR register) and they are independently enabled through CIEx bits of the ICCSR register. After fetching the interrupt vector, the CFx flags can be read to identify the in- terrupt source. The interrupts are synchronized on the counter clock rising edge (Figure 36). During HALT mode, the external interrupts can still be used to wake up the micro (if CIEx bit is set). Figure 36. ART External Interrupt Figure 37. Input Capture Timing Diagram ARTICx PIN CFx FLAG t fCOUNTER INTERRUPT COUNTER t 01h fCOUNTER xxh 02h 03h 04h 05h 06h 07h 04h ARTICx PIN CFx FLAG ICRx REGISTER INTERRUPT |
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