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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU)

6 RESET AND CLOCK CONTROL UNIT (RCCU)

6.1 INTRODUCTION

The Reset and Clock Control Unit (RCCU) com-

prises two distinct sections:

– the Clock Control Unit, which generates and

manages the internal clock signals.

– the Reset/Stop Manager, which detects and

flags Hardware, Software and Watchdog gener-

ated resets.

On ST9 devices where the external Stop pin is

available, this circuit also detects and manages

the externally triggered Stop mode, during which

all oscillators are frozen in order to achieve the

lowest possible power consumption.

6.2 CLOCK CONTROL UNIT

The Clock Control Unit generates the internal

clocks for the CPU core (CPUCLK) and for the on-

chip peripherals (INTCLK). The Clock Control Unit

may be driven by an external crystal circuit, con-

nected to the OSCIN and OSCOUT pins, or by an

external pulse generator, connected to OSCIN

(see Figure 37 and Figure 39).

6.2.1 Clock Control Unit Overview

As shown in Figure 31, a programmable divider

can divide the CLOCK1 input clock signal by two.

The divide-by-two is recommended in order to en-

sure a 50% duty cycle signal driving the PLL mul-

tiplier circuit. The resulting signal, CLOCK2, is the

reference input clock to the programmable Phase

Locked Loop frequency multiplier, which is capa-

ble of multiplying the clock frequency by a factor of

6, 8, 10 or 14; the multiplied clock is then divided

by a programmable divider, by a factor of 1 to 7. By

this means, the ST9 can operate with cheaper,

medium frequency (3-5 MHz) crystals, while still

providing a high frequency internal clock for maxi-

mum system performance; the range of available

multiplication and division factors allow a great

number of operating clock frequencies to be de-

rived from a single crystal frequency.

For low power operation, especially in Wait for In-

terrupt mode, the Clock Multiplier unit may be

turned off, whereupon the output clock signal may

be programmed as CLOCK2 divided by 16. For

further power reduction, a low frequency external

clock connected to the CK_AF pin may be select-

ed, whereupon the crystal controlled main oscilla-

tor may be turned off.

The internal system clock, INTCLK, is routed to all

on-chip peripherals, as well as to the programma-

ble Clock Prescaler Unit which generates the clock

for the CPU core (CPUCLK).

The Clock Prescaler is programmable and can

slow the CPU clock by a factor of up to 8, allowing

the programmer to reduce CPU processing speed,

and thus power consumption, while maintaining a

high speed clock to the peripherals. This is partic-

ularly useful when little actual processing is being

done by the CPU and the peripherals are doing

most of the work.

Figure 31. Clock Control Unit Simplified Block Diagram

Quartz

CK_AF

1/16

1/2

oscillator

source

CLOCK2

CLOCK1

CK_AF

PLL

Clock Multiplier

CPU Clock

Prescaler

CPU Core

Peripherals

CPUCLK

INTCLK

Unit

/Divider

1/4

Standard Timer

CLOCK2/64

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