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ST90135 数据表(PDF) 47 Page - STMicroelectronics |
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ST90135 数据表(HTML) 47 Page - STMicroelectronics |
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47 / 190 page  47/190 ST90158 - REGISTER AND MEMORY MAP (*) Not present on ST90135. Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register description for details. 55 RCCU R240 CLKCTL Clock Control Register 00 R242 CLK_FLAG Clock Flag Register 48, 28 or 08 R246 PLLCONF PLL Configuration Register xx 63 AD0 R240 D0R0 Channel 0 Data Register xx R241 D1R0 Channel 1 Data Register xx R242 D2R0 Channel 2 Data Register xx R243 D3R0 Channel 3 Data Register xx R244 D4R0 Channel 4 Data Register xx R245 D5R0 Channel 5 Data Register xx R246 D6R0 Channel 6 Data Register xx R247 D7R0 Channel 7 Data Register xx R248 LT6R0 Channel 6 Lower Threshold Reg. xx R249 LT7R0 Channel 7 Lower Threshold Reg. xx R250 UT6R0 Channel 6 Upper Threshold Reg. xx R251 UT7R0 Channel 7 Upper Threshold Reg. xx R252 CRR0 Compare Result Register 0F R253 CLR0 Control Logic Register 00 R254 ICR0 Interrupt Control Register 0F R255 IVR0 Interrupt Vector Register x2 Page (Decimal) Block Reg. No. Register Name Description Reset Value Hex. 9 |
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