ST90135 datasheet(94/190 Pages) STMICROELECTRONICS

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ST90158 - I/O PORTS

INPUT/OUTPUT BIT CONFIGURATION (Cont’d)

When Px.n is programmed as an Output:

(Figure 52)

– The Output Buffer is turned on in an Open-drain

or Push-pull configuration.

– The data stored in the Output Master Latch is

copied both into the Input Latch and into the Out-

put Slave Latch, driving the I/O pin, at the end of

the execution of the instruction.

When Px.n is programmed as Bidirectional:

(Figure 53)

– The Output Buffer is turned on in an Open-Drain

or Weak Pull-up configuration (except when dis-

abled in hardware).

– The data present on the I/O pin is sampled into

the Input Latch at the beginning of the execution

of the instruction.

– The data stored in the Output Master Latch is

copied into the Output Slave Latch, driving the I/

O pin, at the end of the execution of the instruc-

tion.

WARNING: Due to the fact that in bidirectional

mode the external pin is read instead of the output

latch, particular care must be taken with arithme-

tic/logic and Boolean instructions performed on a

bidirectional port pin.

These instructions use a read-modify-write se-

quence, and the result written in the port register

depends on the logical level present on the exter-

nal pin.

This may bring unwanted modifications to the port

output register content.

For example:

Port register content, 0Fh

external port value, 03h

(Bits 3 and 2 are externally forced to 0)

A bset instruction on bit 7 will return:

Port register content, 83h

external port value, 83h

(Bits 3 and 2 have been cleared).

To avoid this situation, it is suggested that all oper-

ations on a port, using at least one bit in bidirec-

tional mode, are performed on a copy of the port

struction to the I/O port.

When Px.n is programmed as a digital Alter-

nate Function Output:

(Figure 54)

– The Output Buffer is turned on in an Open-Drain

or Push-Pull configuration.

– The data present on the I/O pin is sampled into

the Input Latch at the beginning of the execution

of the instruction.

– The signal from an on-chip function is allowed to

load the Output Slave Latch driving the I/O pin.

Signal timing is under control of the alternate

function. If no alternate function is connected to

Px.n, the I/O pin is driven to a high level when in

Push-Pull configuration, and to a high imped-

ance state when in open drain configuration.

Figure 53. Bidirectional Configuration

Figure 54. Alternate Function Configuration

OUTPUT MASTER LATCH

INPUT LATCH

OUTPUT SLAVE LATCH

INTERNAL DATA BUS

I/O PIN

WEAK PULL-UP

TTL

(or Schmitt Trigger)

OPEN DRAIN

TO PERIPHERAL

INPUTS AND

INTERRUPTS

INPUT LATCH

FROM

INTERNAL DATA BUS

I/O PIN

OPEN DRAIN

TTL

(or Schmitt Trigger)

PUSH-PULL

PERIPHERAL

OUTPUT

TO PERIPHERAL

INPUTS AND

INTERRUPTS

OUTPUT SLAVE LATCH

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