ST90135 datasheet(80/190 Pages) STMICROELECTRONICS

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ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU)

RESET/STOP MANAGER (Cont’d)

The on-chip Timer/Watchdog generates a reset

condition if the Watchdog mode is enabled

(WCR.WDEN cleared, R252 page 0), and if the

programmed period elapses without the specific

code (AAh, 55h) written to the appropriate register.

The input pin RESET is not driven low by the on-

chip reset generated by the Timer/Watchdog.

When the RESET pin goes high again, 510 oscilla-

tor clock cycles (CLOCK1) are counted before ex-

iting the Reset state (+-1 CLOCK1 period, depend-

ing on the delay between the rising edge of the RE-

SET pin and the first rising edge of CLOCK1). Sub-

sequently a short Boot routine is executed from the

device internal Boot ROM, and control then passes

to the user program.

The Boot routine sets the device characteristics

and loads the correct values in the Memory Man-

agement Unit’s pointer registers, so that these

point to the physical memory areas as mapped in

the specific device. The precise duration of this

short Boot routine varies from device to device,

depending on the Boot ROM contents.

At the end of the Boot routine the Program Coun-

ter will be set to the location specified in the Reset

Vector located in the lowest two bytes of memory.

6.6.1 RESET Pin Timing

To improve the noise immunity of the device, the

RESET pin has a Schmitt trigger input circuit with

hysteresis. In addition, a filter will prevent an un-

wanted reset in case of a single glitch of less than

50 ns on the RESET pin. The device is certain to

reset if a negative pulse of more than 20

µs is ap-

plied. When the RESET pin goes high again, a de-

lay of up to 4

µs will elapse before the RCCU de-

tects this rising front. From this event on, 510 os-

cillator clock cycles (CLOCK1) are counted before

exiting the Reset state (+-1CLOCK1 period de-

pending on the delay between the positive edge

the RCCU detects and the first rising edge of

CLOCK1)

If the ST9 is a ROMLESS version, without on-chip

program memory, the mermory interface ports are

set to external memory mode (i.e Alternate Func-

tion) and the memory accesses are made to exter-

nal Program memory with wait cycles insertion.

Figure 42. Recommended Signal to be Applied on RESET Pin

6.7 EXTERNAL STOP MODE

On ST9 devices provided with an external STOP

pin, the Reset/Stop Manager can also stop all os-

cillators without resetting the device.

To enter Stop Mode, the STOP pin must be forced

to “0” for a minimum of 4 system clock cycles;

while the STOP pin is kept at “0”, the MCU will re-

main in Stop Mode and all context information will

be preserved. During this condition the internal

clock will be frozen in the high state.

When the pin is forced back to “1”, the MCU

resumes execution of the user program after a de-

lay of 255 CLOCK2 periods.

On exiting from Stop mode an interrupt is generat-

ed and the EX_STP bit in CLK_FLAG will be set,

to indicate to the user program that the machine is

exiting from Stop mode.

VRESET

VDD

0.7 VDD

0.3 VDD

µs

Minimum

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