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ST90135 数据表(PDF) 79 Page - STMicroelectronics |
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ST90135 数据表(HTML) 79 Page - STMicroelectronics |
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79 / 190 page ![]() 79/190 ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) 6.6 RESET/STOP MANAGER The Reset/Stop Manager resets the MCU when one of the three following events occurs: – A Hardware reset, initiated by a low level on the RESET pin. – A Software reset, initiated by a HALT instruction (when enabled). – A Watchdog end of count condition. The event which caused the last Reset is flagged in the CLK_FLAG register, by setting the SOF- TRES or the WDGRES bits respectively; a hard- ware initiated reset will leave both these bits reset. The hardware reset overrides all other conditions and forces the ST9 to the reset state. During Re- set, the internal registers are set to their reset val- ues, where these are defined, and the I/O pins are set to the Bidirectional Weak Pull-up mode. Reset is asynchronous: as soon as the RESET pin is driven low, a Reset cycle is initiated. Figure 41. Oscillator Start-up Sequence and Reset Timing VDD MAX VDD MIN OSCIN INTCLK RESET OSCOUT PIN 12ms (5V), 24ms (3V) VR02085A 9 |
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