ST90135 datasheet(114/190 Pages) STMICROELECTRONICS

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ST90158 - MULTIFUNCTION TIMER (MFT)

MULTIFUNCTION TIMER (Cont’d)

9.2.5 Interrupt and DMA

9.2.5.1 Timer Interrupt

The timer has 5 different Interrupt sources, be-

longing to 3 independent groups, which are as-

signed to the following Interrupt vectors:

Table 23. Timer Interrupt Structure

The three least significant bits of the vector pointer

address represent the relative priority assigned to

each group, where 000 represents the highest pri-

ority level. These relative priorities are fixed by

hardware, according to the source which gener-

ates the interrupt request. The 5 most significant

bits represent the general priority and are pro-

grammed by the user in the Interrupt Vector Reg-

ister (T_IVR).

Each source can be masked by a dedicated bit in

the Interrupt/DMA Mask Register (IDMR) of each

timer, as well as by a global mask enable bit (ID-

MR.7) which masks all interrupts.

If an interrupt request (CM0 or CP0) is present be-

fore the corresponding pending bit is reset, an

overrun condition occurs. This condition is flagged

in two dedicated overrun bits, relating to the

Comp0 and Capt0 sources, in the Timer Flag Reg-

ister (T_FLAGR).

9.2.5.2 Timer DMA

Two Independent DMA channels, associated with

Comp0 and Capt0 respectively, allow DMA trans-

fers from Register File or Memory to the Comp0

File or Memory). If DMA is enabled, the Capt0 and

Comp0 interrupts are generated by the corre-

sponding DMA End of Block event. Their priority is

set by hardware as follows:

– Compare 0 Destination

—

Lower Priority

– Capture 0 Source

—

Higher Priority

The two DMA request sources are independently

maskable by the CP0D and CM0D DMA Mask bits

in the IDMR register.

The two DMA End of Block interrupts are inde-

pendently enabled by the CP0I and CM0I Interrupt

mask bits in the IDMR register.

9.2.5.3 DMA Pointers

The 6 programmable most significant bits of the

DMA Counter Pointer Register (DCPR) and of the

DMA Address Pointer Register (DAPR) are com-

mon to both channels (Comp0 and Capt0). The

Comp0 and Capt0 Address Pointers are mapped

as a pair in the Register File, as are the Comp0

and Capt0 DMA Counter pair.

In order to specify either the Capt0 or the Comp0

pointers, according to the channel being serviced,

the Timer resets address bit 1 for CAPT0 and sets

it for COMP0, when the D0 bit in the DCPR regis-

ter is equal to zero (Word address in Register

File). In this case (transfers between peripheral

registers and memory), the pointers are split into

two groups of adjacent Address and Counter pairs

respectively.

For peripheral register to register transfers (select-

ed by programming “1” into bit 0 of the DCPR reg-

ister), only one pair of pointers is required, and the

pointers are mapped into one group of adjacent

positions.

The DMA Address Pointer Register (DAPR) is not

used in this case, but must be considered re-

served.

Figure 61. Pointer Mapping for Transfers

between Registers and Memory

Interrupt Source

Vector Address

COMP 0

COMP 1

xxxx x110

CAPT 0

CAPT 1

xxxx x100

Overflow/Underflow

xxxx x000

Address

Pointers

Comp0 16 bit

Addr Pointer

YYYYYY11(l)

YYYYYY10(h)

Capt0 16 bit

Addr Pointer

YYYYYY01(l)

YYYYYY00(h)

DMA

Counters

Comp0 DMA

16 bit Counter

XXXXXX11(l)

XXXXXX10(h)

Capt0 DMA

16 bit Counter

XXXXXX01(l)

XXXXXX00(h)

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