T80C5112-RKSCV datasheet(63/97 Pages) ATMEL

63 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

Reset Value=X000 0000b

Table 36. ADCLK Register

ADCLK (S:F2h)

ADC Clock Prescaler

Reset Value: 0000 0000b

Table 37. ADDH Register

ADDH (S:F5h Read Only)

ADC Data High byte register

Read only register

Reset Value: 00h

ADEN

Enable/Standby Mode

Set to enable ADC.

Clear for Standby mode (power dissipation 1 uW).

ADEOC

End Of Conversion

Set by hardware when ADC result is ready to be read. This flag can generate an interrupt.

Must be cleared by software.

ADSST

Start and Status

Set to start an A/D conversion.

Cleared by hardware after completion of the conversion.

2-0

SCH2:0

Selection of channel to convert

see Table 34.

SELREF

PRS 6

PRS 5

PRS 4

PRS 3

PRS 2

PRS 1

PRS 0

Bit Number Bit Mnemonic

Description

SELREF

Selection and activation of the internal 2.4V voltage reference

Set to enable the internal voltage reference.

Clear to disable the internal voltage reference.

6-0

PRS6:0

Clock Prescaler

fCONV_CK =fCkADC / (2 * PRS)

if PRS=0, fCONV_CK =fCkADC / 256

ADAT 9

ADAT 8

ADAT 7

ADAT 6

ADAT 5

ADAT 4

ADAT 3

ADAT 2

Bit Number Bit Mnemonic

Description

7-0

ADAT9:2

ADC result

bits 9-2

Bit Number Bit Mnemonic

Description

T80C5112-RKSCV 数据表(PDF) 63 Page - ATMEL Corporation

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