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T80C5112-RKSCV 数据表(PDF) 60 Page - ATMEL Corporation |
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T80C5112-RKSCV 数据表(HTML) 60 Page - ATMEL Corporation |
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60 / 97 page  60 Rev. B - November 10, 2000 Preliminary T80C5112 Figure 28. ADC Description Figure 29 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer to the Section ÒAC CharacteristicsÓ of the T80C5112 datasheet. Figure 29. Timing Diagram NOTE: Tsetup = 4 us 14.4. ADC Converter Operation A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). The busy flag ADSST(ADCON.3) remains set as long as an A/D conversion is running. After completion of the A/D conversion, it is cleared by hardware. When a conversion is running, this flag can be read only, a write has no effect. AIN0/P4.0 AIN1/P4.1 AIN2/P4.2 AIN3/P4.3 AIN4/P4.4 AIN5/P4.5 AIN6/P4.6 AIN7/P4.7 000 001 010 011 100 101 110 111 SCH2 ADCON.2 SCH0 ADCON.0 SCH1 ADCON.1 CONV_CK ADEN ADCON.5 ADSST ADCON.3 ADEOC ADCON.4 ADC Interrupt Request EADC IE1.1 CONTROL AVSS Sample and Hold ADDH Vref R/2R DAC 8 10 + - ADDL 2 SAR ADCIN VAGND SELREF ADCLK.7 2.4V VADREF ADEN ADCON.5 ADEN ADSST ADEOC TSETUP TCONV CONV_CK |
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