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ADE3800XT 数据表(PDF) 115 Page - STMicroelectronics |
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ADE3800XT 数据表(HTML) 115 Page - STMicroelectronics |
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115 / 138 page ![]() 115/138 ADE3800 Register Description by Block ANA_LVDSANA1 0061 [7:6] R/W 00 Bit 3 Data Interface Delay Adjustment, see Bit 0 [5:4] R/W Bit 2 Data Interface Delay Adjustment, see Bit 0 [3:2] R/W Bit 1 Data Interface Delay Adjustment, see Bit 0 [1:0] R/W Bit 0 Data Interface Delay Adjustment 0*: 0ps (normal) 1: 90ps 2: 210ps 3: 460ps ANA_LVDSANA2 0062 [7] C0 PLL power control 0: on 1*: off [6] PLL Global Data Interface Delay 0: no delay 1*: delay (normal) [5:4] R/W Bit 6 Data Interface Delay Adjustment, see Bit 0 [3:2] R/W Bit 5 Data Interface Delay Adjustment, see Bit 0 [1:0] R/W Bit 4 Data Interface Delay Adjustment, see Bit 0 ANA_LVDSANA4 0064 [6:4] R/W 01 LVDS Clock Skew LSB = 135ps (typ) [3] LVDS Clock Skew Enable 0*: no delay (normal) 1: delay [2] LVDSclkout1 output polarity 0*: normal 1: invert [1] LVDSclkout0 output polarity 0*: normal 1: invert [0] LVDS & RSDS Master Power Control (Overrides ANA_LVDSANA5[7], ANA_LVDSANA6[7], and ANA_LVDSANA2[7]) Table 41: LVDS/RSDS Registers (Sheet 2 of 5) Register Name Address Bits Mode Rst Description |
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