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ADE3800XT 数据表(PDF) 118 Page - STMicroelectronics |
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ADE3800XT 数据表(HTML) 118 Page - STMicroelectronics |
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118 / 138 page  Register Description by Block ADE3800 118/138 ANA_LVDS_DLY_0 006A [6:4] R/W 33 LVDSDLYCH1 LVDS/RSDS output skew adjust 0: 176ps (typ) 1: 104ps (typ) 2: 73ps (typ) 3*: 50ps (typ) 4: 39ps (typ) 5: 18ps (typ) 6: 7ps (typ) 7: no delay (normal) [2:0] LVDSDLYCH0 ANA_LVDS_DLY_1 006B [6:4] R/W 33 LVDSDLYCLK0 [2:0] LVDSDLYCH2 ANA_LVDS_DLY_2 006C [6:4] R/W 33 LVDSDLYCH4 [2:0] LVDSDLYCH3 ANA_LVDS_DLY_3 006D [6:4] R/W 33 LVDSDLYCH6 [2:0] LVDSDLYCH5 ANA_LVDS_DLY_4 006E [6:4] R/W 33 LVDSDLYCH7 [2:0] LVDSDLYCLK1 ANA_RSDS_DLY_0 0070 [6:4] R/W 33 RSDSDLYCH1 [2:0] RSDSDLYCH0 ANA_RSDS_DLY_1 0071 [6:4] R/W 33 RSDSDLYCH3 [2:0] RSDSDLYCH2 ANA_RSDS_DLY_2 0072 [6:4] R/W 33 RSDSDLYCH5 [2:0] RSDSDLYCH4 ANA_RSDS_DLY_3 0073 [6:4] R/W 33 RSDSDLYCH7 [2:0] RSDSDLYCH6 ANA_RSDS_DLY_4 0074 [6:4] R/W 33 RSDSDLYCH9 [2:0] RSDSDLYCH8 ANA_RSDS_DLY_5 0075 [6:4] R/W 33 RSDSDLYCH11 [2:0] RSDSDLYCH10 ANA_RSDS_DLY_6 0076 [6:4] R/W 33 RSDSDLYCH13 [2:0] RSDSDLYCH12 ANA_RSDS_DLY_7 0077 [6:4] R/W 33 RSDSDLYCH15 [2:0] RSDSDLYCH14 Table 42: LVDS / RSDS Power Configurations State PLL LVDS Output RSDS Output ANA_LVDSANA4[0] Master Power Ctrl ANA_LVDSANA5[5] Output Mode Sel ANA_LVDSANA2[7] PLL Power Ctrl All Off off off off 1 X X LVDS On on on off 0 1 0 RSDS On off off on 0 0 X Table 41: LVDS/RSDS Registers (Sheet 5 of 5) Register Name Address Bits Mode Rst Description |
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