ADE3800XT datasheet(121/138 Pages) STMICROELECTRONICS

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ADE3800

It is therefore strongly recommended to wait until the I2CBKT transfer in progress is completed,

before initiating any I2C access other than polling the I2CBKT_STATUS register.

Note:

In case of need, a clean way to stop the current I2CBKT transfer is to write I2CBKT_CTRL[0] to 0.

EXAMPLE

Fill every other byte of the entire OSD_RAM with a byte previously stored at address 4700:

I2CBKT_SRC_L = 00, I2CBKT_SRC_U = 47: start address where the data is located

I2CBKT_SRCLEN_L = 01, I2CBKT_SRCLEN_U = 00: only 1 byte to transfer from source

Table 44: I2C Block Transfer Registers

Addr

Bits

Mode

Rst

Description

I2CBKT_INC

0021

[7:0]

R/W

destination address increment, 1 to 255 allowed

I2CBKT_SRCLEN_L

0022

[7:0]

R/W

length of source block, in bytes.

If source length < destination length, the source data is

repeated

I2CBKT_SRCLEN_U

0023

[7:0]

R/W

I2CBKT_DESLEN_L

0024

[7:0]

R/W

length of block transfer, in bytes.

Include effect of increment if I2CBKT_CTRL[3:2] = 1

I2CBKT_DESLEN_U

0025

[7:0]

R/W

I2CBKT_SRC_L

0026

[7:0]

R/W

source starting address

I2CBKT_SRC_U

0027

[7:0]

R/W

I2CBKT_DES_L

0028

[7:0]

R/W

destination starting address

I2CBKT_DES_U

0029

[7:0]

R/W

I2CBKT_CTRL

002A

[6:4]

R/W

transfer start condition select (level sensitive)

0*: immediate

1: when in_henab = 0

2: when out_henab = 0

3: when in_venab = 0

4: when out_venab = 0

5: tcon_i2c_transfer = 1 (refer to TCON_CTRL[3:2])

[3:2]

R/W

increment mode

0*: source + 1, dest + 1

1: source + 1, dest + inc (as set in I2CBKT_INC)

2: reserved

3: reserved

[1]

R/W

0*: one way transfer from source to destination

1: swap source and destination

[0]

R/W

0*: end of transfer, or stop transfer in progress

1: start transfer according to condition bits [6:4]

Must be set and cleared by software

I2CBKT_PULSE

002B

[7:4]

R/W

read pulse width (reserved)

[3:0]

R/W

write pulse width (reserved)

I2CBKT_STATUS

002C

[0]

Transfer status

0*: block transfer completed

1: block transfer in progress

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