ADE3800XT datasheet(120/138 Pages) STMICROELECTRONICS

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4.21 I²C Block Transfer (I2CBKT)

The block transfer function allows the internal I²C parallel bus to be driven by an xclk state machine

to perform fast block transfers between internal addresses without any MCU software overhead.

Transfer speed is approximately 2MByte per second under typical conditions.

4.21.1 Transfer Setup and Start

Writing the bit I2CBKT_CTRL[0] to 1 initiates the transfer, according to all source and destination

parameters (addresses, length):

● Length for source is programmable to allow repeated patterns/fills, such as filling an entire area

with the same byte(s)

● An increment register for the destination allows to fill it only every n

th byte

Depending on the increment value, the destination length must be programmed as follows:

● If I2CBKT_CTRL[3:2]=0 (or =1 with I2CBKT_INC=1): DESLEN = nb of bytes to transfer

● If I2CBKT_CTRL[3:2]=1 with I2CBKT_INC>1: DESLEN = (nb of bytes to transfer * INC) - 1

The transfer can either take place immediately, or be initiated by a number of selectable events

coming from SMUX or TCON, as programmed in I2CBKT_CTRL[6:4].

Transfers can occur between RAM or registers or both, but cannot take place in the own registers of

the I2CBKT block (refer to Section 4.21.3: Concurrent I2C Transfers below).

Source and destination addresses cannot overlap.

Data can be either transferred from source to destination (one way) or swapped between them,

depending on I2CBKT_CTRL[1].

4.21.2 Transfer Progress

The status bit I2CBKT_STATUS[0] is set to 1 by hardware as soon as the transfer actually starts,

and falls back to 0 when the transfer is completed.

Note:

It is the software’s duty to write I2CBKT_CTRL[0] to 0 upon transfer completion, before preparing

any new subsequent I2CBKT transfer.

4.21.3 Concurrent I2C Transfers

While the I2CBKT block is operating, only I2C accesses from MCU to the I2CBKT registers listed

below are allowed: any I2C access to other adresses will take priority and stop the I2CBKT transfer

in progress in an unknown state (there is no way to tell which bytes have been transferred up to that

point).

PWM_STEP_DELAY

01A8

R/W

[7:0]

In smooth change mode, the number of

cycles skipped before the period/duty

registers are incremented/decremented

PWM_CYCLES_PER_FRAME_L

PWM_CYCLES_PER_FRAME_U

01A9

01AA

R/W

[7:0]

The number of cycles per frame in frame lock

mode when not using the internally generated

cycles per frame from a previous free-running

mode

Table 43: PWM Registers (Sheet 2 of 2)

Addr

Mode

Bits

Default

Description

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