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ADE3800XT 数据表(PDF) 122 Page - STMicroelectronics |
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ADE3800XT 数据表(HTML) 122 Page - STMicroelectronics |
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122 / 138 page  Register Description by Block ADE3800 122/138 I2CBKT_DES_L = 00, I2CBKT_DES_U = 17: destination start address (OSD_RAM) where the data will be written I2CBKT_INC = 02: skip every other byte I2CBKT_DESLEN_L = FF, I2CBKT_DESLEN_U = 5F: (46FF-1700+1) = 12288 bytes to transfer means destination length = (12288 x increment) - 1 = 5FFF I2CBKT_CTRL = 05: immediate transfer with source+1 and destination+2 4.22 I²C Registers and RAM Addresses The I2C own address of the device (also called “ADE_ID”) is A8h. 4.22.1 I2C Transfer Format All I2C addresses, registers and RAM, are 16-bit wide. Address LSB must be transferred first, followed by MSB then the data, as in the following I2C write access example: 4.22.2 Dedicated RAM Areas per Block 4.22.3 Multi-byte Registers Data are read back in the order of how they were written. All values spread out over several registers are organised as follows: Start ADE_ID (A8) Acka a. All Ack bits are returned by the device. Register Address LSB Ack Register Address MSB Ack Data 1 Ack ...further data... Stop Table 45: I²C RAM Addresses Name Description Block Clock Conditiona a. The relevant clock condition must be met to grant access to that block’s registers and RAM. Start Addr End Addr Size Size in Bytes GAM_R Gamma Red LUT GAMMA dotclk >= sclk 1000 10FF 256x8b 256 GAM_G Gamma Green LUT 1100 11FF 256x8b 256 GAM_B Gamma Blue LUT 1200 12FF 256x8b 256 OSD_RAM Characters RAM Area OSD 1700 46FF 4096x24b 12288 OSD_CLUT Color LUT 4700 47FF 64x32b 256 SCL_RAM_1 Line Buffers SCL sclk >= xclk 9000 A700 1024x42b n/a SCL_RAM_2 A800 BFFF 1024x42b n/a OMUX In RSDS Mode onlyb b. In RSDS mode: OMUX uses this RAM area for internal computation purposes, it should not be otherwise modified by any means. In LVDS mode, this RAM is free of use, and can be used as a temporary storage or working area for example. OMUX dotclk >= sclk E300 F1FF 640x48b 3840 |
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