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ADE3800SXT 数据表(PDF) 59 Page - STMicroelectronics

部件名 ADE3800SXT
功能描述  Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters
PDF  138 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ADE3800SXT 数据表(HTML) 59 Page - STMicroelectronics

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ADE3800
Register Description by Block
Note:
Upscaling and downscaling can be simultaneously combined horizontally and vertically.
4.11 Pattern Generator (PGEN)
The PGEN block can generate graphic patterns to support debug and test tasks for LCD panels
such as horizontal or vertical bicolor stripes, bicolor checkers, color bars, gray scales or color
scales. It is also possible to pass through the RGB signal coming from the SCL block.
Note:
The PGEN block is located before the sRGB color management block.
4.11.1 Overview
The following features of the PGEN block overlap each other like layers, defining display priorities:
Bars (lowest display priority)
Cells and Grids
Borders
TCON Window Control (highest display priority)
Bars and cells are freely programmable in size and independently of each other.
A border is a horizontal or vertical borderline. If enabled, it has priority over the above settings.
Above all, aTCON window, if enabled, restrains all PGEN settings to a given display area.
H_KERNEL_1
0A11
00
00
FE
FE
H_KERNEL_2
0A12
00
00
FA
FC
H_KERNEL_3
0A13
00
00
F9
FB
H_KERNEL_4
0A14
00
00
FF
00
H_KERNEL_5
0A15
00
10
10
0F
H_KERNEL_6
0A16
20
20
26
24
H_KERNEL_7
0A17
40
30
39
38
H_KERNEL_8
0A18
40
40
41
40
H_KERNEL_NORM
0A19
40
40
40
40
V_KERNEL_0
0A1A
00
00
FB
FA
V_KERNEL_1
0A1B
00
00
F9
FA
V_KERNEL_2
0A1C
00
00
FF
FE
V_KERNEL_3
0A1D
00
10
10
0D
V_KERNEL_4
0A1E
00
20
23
22
V_KERNEL_NORM
0A1F
40
40
40
40
Register
Address
No Scaling
Down Scaling
Up Scaling
Nearest Neighbor
Bilinear
“-0.7” Cubic
“-0.5” Cubic



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