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ADE3800SXT 数据表(PDF) 23 Page - STMicroelectronics |
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ADE3800SXT 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 138 page  23/138 ADE3800 Register Description by Block The ADC clamp signal is generated in digital circuitry. 4.3.2.2 SOG Lock State Set: ● ANA_ADC_SOG_1[0] remains 0, ● ANA_ADC_GRN_2[1] = 0 (ADC clamp on; must be the same as ANA_ADC_SOG_1[3]). ● ANA_ADC_SOG_1[3] = 0 (disable SOG clamp pull down current), This enables the ADC Clamp circuit and disables the SOG Clamp (this is the recommended order – it is better to have overlap than no clamp at all). The comparators will continue to compare the input signal with the reference voltages and provide a correct SOG signal. Comparator threshold voltages can be adjusted to optimize noise immunity if necessary. Figure 4: Initial SOG Clamp Phase ADCSOG1[0] = 0 (pwdnSOG) ADCSOG1[3] (enSOG) = ADCGRN2[1] = 1 |
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