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ADE3800SXT 数据表(PDF) 66 Page - STMicroelectronics |
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ADE3800SXT 数据表(HTML) 66 Page - STMicroelectronics |
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66 / 138 page  Register Description by Block ADE3800 66/138 EXAMPLES All examples assume that the display panel size is 1280x1024 and no pattern is preset, therefore: ● PGEN_X_TOT_L = 00, PGEN_X_TOT_H = 05 ● PGEN_Y_TOT_L = 00, PGEN_Y_TOT_H = 04 ● All other registers are 00 ● A stable picture is being displayed Example 1 PGEN_GRID0 = PGEN_GRID7 = 00 generated pattern is enabled on all 8 cells of grid 0 (top) and grid 7 (bottom) PGEN_GRID1..6 = 7E generated pattern is enabled on 1st and 8th cells only of grid 1 thru 6 PGEN_GRID_X_L = 1280 / 8 cells per grid across screen = A0, PGEN_GRID_X_H = 00 PGEN_GRID_Y_L = 1024 / 8 lines across screen = 80, PGEN_GRID_Y_H = 00 PGEN_P0_MODE = 00 color C0 uses 1 bar (bar 0) only PGEN_P0_COLOR_R_C1 061D R/W [7:0] 00 color C1 – red PGEN_P0_SEQ_COL0_COL1 061E R/W [6:4] 00 bar 0: R G B color mask R/W [2:0] bar 1: R G B color mask PGEN_P0_SEQ_COL2_COL3 061F R/W [6:4] 00 bar 2: R G B color mask R/W [2:0] bar 3: R G B color mask PGEN_P0_SEQ_COL4_COL5 0620 R/W [6:4] 00 bar 4: R G B color mask R/W [2:0] bar 5: R G B color mask PGEN_P0_SEQ_COL6_COL7 0621 R/W [6:4] 00 bar 6: R G B color mask R/W [2:0] bar 7: R G B color mask PGEN_P0_WDTH_L PGEN_P0_WDTH_U 0622 0623 R/W R/W [7:0] [3:0] 00 00 bar width, in pixels PGEN_P0_HGHT_L PGEN_P0_HGHT_U 0624 0625 R/W R/W [7:0] [3:0] 00 00 bar height, in lines PGEN_P0_WDTH_X_OFFSET_L PGEN_P0_WDTH_X_OFFSET_U 0626 0627 R/W R/W [7:0] [3:0] 00 00 bar horizontal offset, in pixels PGEN_P0_HGHT_Y_OFFSET_L PGEN_P0_HGHT_Y_OFFSET_U 0628 0629 R/W R/W [7:0] [3:0] 00 00 bar vertical offset, in lines PGEN_P0_GRADDELTA_B 062A R/W [7:0] 00 blue gradient delta PGEN_P0_GRADDELTA_G 062B R/W [7:0] 00 green gradient delta PGEN_P0_GRADDELTA_R 062C R/W [7:0] 00 red gradient delta PGEN_P0_GRADSTEP_X 062D R/W [7:0] 00 gradient horizontal step, in pixels PGEN_P0_GRADSTEP_Y 062E R/W [7:0] 00 gradient vertical step, in lines Table 25: Pattern Generator Registers (Sheet 3 of 3) Register Name Addr Mode Bits Rst Description |
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