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数据搜索系统，热门电子元器件搜索 |
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ADE3800SXT 数据表(PDF) 102 Page - STMicroelectronics |
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ADE3800SXT 数据表(HTML) 102 Page - STMicroelectronics |
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102 / 138 page  Register Description by Block ADE3800 102/138 4.18 Timing Controller (TCON) The Timing Controller block provides all output timing signals for panel applications. Features include: ● comparator, pulse and window functions ● LC polarity inversion function generator ● separate logic and output crossbars ● out_HSync, out_vsync and out_enab generation ● register shadowing Figure 21: Output timing (hcount,vcount) destination image controlled by scaler phase generator origin_h/vpos and h/v scale_factor (out_henab_set,out_venab_set) (0,0) background color out_htotal out_vtotal_min out_vtotal_max variable length last line scaled image blanking free run sequencer armed for reset (out_henab_reset,out_venab_reset) min 28 min 28 SCALED IMAGE min 32 min 32 variable length last line terminated by SMUX vtrig delayed by SCL_TRIGGER_DLY |
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