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ADE3800SXT 数据表(PDF) 107 Page - STMicroelectronics |
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ADE3800SXT 数据表(HTML) 107 Page - STMicroelectronics |
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107 / 138 page  107/138 ADE3800 Register Description by Block TCON_INV_1 0B03 [7] R/W 00 invert output osd_lut [6] R/W invert output pgen [5] R/W invert output gamma_2 [4] R/W invert output gamma_1 [3] R/W invert output srgb [2] R/W invert output out_enab [1] R/W invert output out_vsync [0] R/W invert output out_HSync TCON_SHADOW_CTRL 0B04 [7:4] 00 shadow target 00*: comp 0 01: comp 1 02: comp 2 03: comp 3 04: pulse 0 05: pulse 1 06: pulse 2 07: pulse 3 08: pulse 4 09: pulse 5 0A: window 0 0B: window 1 0C: window 2 0D: window 3 0E: polarity 0F: reserved [3:2] R/W tcon shadow event selection 0*: (hcount == 0) && (vcount == 0) 1: (hcount == 0) 2: srtd0 3: srtd1 [1] R/W shadow transfer enable - set to transfer at next event - bit is automatically cleared when trans- fer is complete [0] R/W shadow enable TCON_SHADOW_BUF_0 0B05 [7:0] R/W 00 shadow buffer 0 TCON_SHADOW_BUF_1 0B06 [4:0] R/W 00 shadow buffer 1 TCON_SHADOW_BUF_2 0B07 [7:0] R/W 00 shadow buffer 2 TCON_SHADOW_BUF_3 0B08 [7:0] R/W 00 shadow buffer 3 Table 39: Register Map (Sheet 2 of 7) Register Name Addr. Bits Mode Rst Description |
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