TAS3218IPZP datasheet(33/78 Pages) TI

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I2C Slave Mode Operation

TAS3218

www.ti.com ....................................................................................................................................................................................................... SLES235 – JULY 2008

The I2C slave mode is the mode that is used to change configuration parameters during operation and perform

program and coefficient downloads from a master device. The latter can be used to replace the I2C master mode

EEPROM download.

The TAS3218 uses the slave mode to load the memory contents for the:

• Micro program memory

• Micro extended memory

• DSP program memory

• DSP coefficient memory

• DSP data memory

• Update coefficient and other control values

• Read status flags

The TAS3218 support both random and sequential I2C transactions. The TAS3218 I2C slave address is

011010X, where the first 6 bits are the TAS3218 device address and the final 1 bit is set by the TAS3218 internal

microprocessor at power-up. The internal microprocessor derives the last bit from an external pin (pin CS) which

is pulled up or down to create two unique addresses for control of multiple-TAS3218 part applications. The

pulldown resistance of CS creates a default 00 address when no connection is made to the pin.

The TAS3218 I2C block does respond to the broadcast address (00h).

NOTE:

When acting as an I2C slave, data rate transfer is determined by the master device on

the bus. However, the setting of I2C parameter N at sub-address 0x01 does play a

role in setting the maximum possible data transfer rate. In the I2C slave mode, bit

rates other than (and including) the I2C-specific 100 Kbps and 400 Kbps bit rates can

be obtained, but N must always be set so that the over-sample clock into the I2C

master and slave controllers is at least a factor of 20 higher in frequency than SCL.

N = 0 is a special case. When N = 0, a mode is enabled that detects I2C frames and enables the TAS3218 I2C

interface to reset and continue operation after receiving an invalid I2C frame.

Table 7.

I2C Slave Addresses

SLAVE ADDRESS

0x68/69

0x6A/6B

Table 8.

I2C Master Addresses

SLAVE ADDRESS

0xA0/A1

0xA2/A3

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