TAS3218IPZP datasheet(27/78 Pages) TI

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TAS3218

www.ti.com ....................................................................................................................................................................................................... SLES235 – JULY 2008

GPIO1 Pin Function

• After RESET or powerup initialization, if no EEPROM is present, a memory error occurs, or SDA and SCL are

pulled LOW for 1 ms, then TAS3218 will disable the master I2C interface and enable the slave I2C interface

initialization, to load the slave default configuration.

–

When GPIO1 has been pulled HIGH through a 1020-k resistor the TAS3218 will then initialize in the

default configuration with the serial data outputs not active. Once the TAS3218 has completed its default

initialization procedure, with the status register updated and the I2C slave interface enabled, then the

GPIO1 pin will become an output and will be driven LOW. Following the High to Low transition of the

GPIO1 pin, the system controller can access the TAS3218 through the I2C interface and read the status

If a memory read error occurs the TAS3218 will report the error in the status register.

–

When GPIO1 has been pulled LOW through a 1020-k resistor to permit a simple functional device test, the

GPIO1 pin can be pulled low using external logic and a 1020-k resistor. In this case, once the TAS3218

has completed its default test initialization procedure, with the status register updated and the I2C slave

interface enabled, then the TAS3218 will stream audio from the input SDIN1 to outputs SDOUT1 and

SDOUT2.

At this point the GPIO1 pin will become an output and will be driven LOW. If the external logic is no longer

driving the GPIO1 pin low after the load has completed (100 ms following a RESET if no EEPROM is

present), then the state of the GPIO1 pin can be observed. At this point the system controller can access

the TAS3218 through the I2C interface and read the status register to determine the load status.

NOTE:

If the GPIO1 pin state is not observed, the only indication that the device has

completed its initialization procedure is that the TAS3218 will stream audio and the

I2C slave interface has been enabled.

NOTE:

Some I2C masters will hang when they receive a NAC during an I2C transaction.

• Once the TAS3218 has been programmed either through a successful boot load or via slave I2C download,

the operation of GPIO1 can be programmed to be an input or an output.

General Purpose I/O Ports (GPIOs)

In I2C slave mode, the GPIO ports can be used as true general-purpose ports. Each port can be individually

programmed, via the I2C bus, to be either an input or an output port. The default assignment for all GPIO ports,

in I2C slave mode, is an input port.

When a given GPIO port is programmed as an output port, by setting the appropriate bit in the bit field GPIODIR

of subaddress 0x0C to logic 1, the logic level output is set by the logic level programmed into the appropriate bit

in bit field GPIO IN OUT. The I2C bus then controls the logic output level for those GPIO ports assigned as

output ports. When a given GPIO port is programmed as an input port by setting the appropriate bit in bit field

GPIODIR to logic 0, the logic input level into the GPIO port is written to the appropriate bit in bit field GPIO IN

OUT. The I2C bus can then be used to read bit field GPIO IN OUT to determine the logic levels at the input GPIO

ports. Whether a given bit in the bit field GPIO IN OUT is a bit to be read via the I2C bus or a bit to be written to

via the I2C bus is strictly determined by the corresponding bit setting in bit field GPIODIR.

In the I2C slave mode, the GPIO input ports are read every GPIOMICROCOUNT Micro Clocks, as was the case

in the I2C master mode. However, parameter GPIO_samp_int does not have a role in the I2C slave mode. If a

GPIO port is assigned as an output port, a logic 0 bit value is supplied by the TAS3218 for this GPIO port in

response to a read transaction at subaddress 0x0C.

If the GPIO ports are left in their power turn on default state, they are input ports with a weak pull-up on the input

to VDSS.

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