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TAS3218IPZP 数据表(PDF) 18 Page - Texas Instruments

部件名 TAS3218IPZP
功能描述  DIGITAL AUDIO PROCESSOR WITH ANALOG INTERFACE
PDF  78 Pages
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

TAS3218IPZP 数据表(HTML) 18 Page - Texas Instruments

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TAS3218
SLES235 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com
Table 2. Relationship of M8051 SFR Register Map With I2C Registers
RST:
Module reset
0:
Normal operation
1:
Reset SPDIF-TX module (default)
CP:
Copy permit
0:
Copy prohibit (default)
1:
Copy permit
EMP:
Pre-emphasis
0:
No pre-emphasis (default)
1:
50/15 s 2-channel pre-emphasis
CATEGORY:
Category code 7-bit device category code. Default: 0101010
(digital sound processor)
L:
Generation status
0:
Generation 1 or higher (default)
1:
Original
SR:
Sampling rate
00:
44.1 kHz
01:
48 kHz (default)
10:
Reserved
11:
32 kHz
VL:
Validity for left channel
0:
Left channel data is valid (default)
1:
Left channel data is invalid
VR:
Validity for right channel
0:
Right channel data is valid (default)
1:
Right channel data is invalid
SRCNUM:
Source channel number
0000:
Not specified
0001:
1
0010:
2 (default)
0011:
3
. . .
1000:
8
CLKAC:
Clock accuracy
00:
Level II, 1000 ppm
01:
Level III, variable pitch shifted
10:
Level I, 50 ppm (default)
11:
Reserved
WORDLEN:
Sample bit size
0000:
24 bits (default)
0001:
23 bits
0010:
22 bits
. . .
20 bits
0100:
. . .
1000:
16 bits
Others:
Reserved
I2C Register Map for SPDIF
Figure 15 shows system accessible I2C register mapping for controlling the SPDIF module. The mute control
(MTE) uses the same control bits for controlling SDOUT2 mute at subaddress 0x09 and the module reset (RST)
is mapped to subaddress 0x10 together with other power down control bits. Other control bits are mapped to
subaddress 0x16.
18
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Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): TAS3218



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