TAS3218IPZP datasheet(17/78 Pages) TI

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Start of Channel Status Block

Audio Data

Preamble

Bits: 0

3 4

7 8

27 28 29 30 31

Aux Data LSB

MSB V U C P

Channel A

Channel B

Validity Data

User Data

Parity Bit

Frame 191

Frame 0

Frame 1

One Sub-Frame

Channel Status Data

TAS3218

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Figure 14. SPDIF Frame Format

SPDIF Encoder Operation

The SPDIF encoder performs the multiplexing of audio, channel status, user, and validity flag. It also performs

bi-phase mark encoding of the multiplexed data stream. Audio data for both left and right channels from the DAP

are latched at the rising edge of the internal LRCLK, which marks the beginning of next sample cycle. The SPDIF

encoder then multiplexes these samples with internally generated preambles, channel status, user data, validity

flag, and parity. The channel status and validity flag are generated based on the settings in the SPDIF control

registers while the user data is fixed to all zero. The bi-phase mark encoded signal is then output starting at the

next rising edge of the internal LRCLK. The generated SPDIF stream is fixed to consumer mode linear audio

PCM format.

While the RESET input is low, the transmitter output, SPDIF_OUT, is forced to logic low level. Upon setting

RESET high, the SPDIF encoder will remain inactive until the module reset is removed by writing 0 to the RST

bit of the control register. Then this module will wait for synchronization with the internal frame clock and starts

encoding audio data. It is recommended to set all other SPDIF control register bits before releasing the module

reset.

Transmitter Control Register

Table 1 shows the M8051 SFR register map for the S/PDIF module control.

Table 1. M8051 SFR Register Map

ADDR

xx00

RST

EMP

xx01

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