TAS3218IPZP datasheet(20/78 Pages) TI

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Analog Audio Interface

Stereo Analog to Digital Converter

TAS3218

SLES235 – JULY 2008 ....................................................................................................................................................................................................... www.ti.com

Table 3. Specification Coverage for TAS3218(1)

SPECIFICATION

SECTION

SUPPORTED

REMARKS

Interface Format (4)

Yes

Auto frame formatting

IEC60958-1

Channel Status (5)

Yes

First 2 bits fixed to 00. (consumer, linear PCM)

Mode 1 (software info delivery using

IEC958-2

Bits 28191 are fixed to all zero.

b32191 of channel stat) (4.2.2.14.2.2.3)

Channel Status General (5.1)

Yes

First channel status bit fixed to 0.

b01:

Fixed (00)

b2:

Channel Status Application (5.2.1) –

Yes

Byte0 (control)

b35:

b67:

Fixed (00)

Category code is register settable, with default value

Channel Status Application (5.2.2) –

Yes, with restriction

0101010L (Digital Sound Processor), but user data is

Byte1 (category)

fixed to all zero.

b1619:

Channel Status Application (5.2.2)

Yes

Byte2 (source and channel number)

b2023:

H/W auto set (1 for left, 2 for right channel)

b2427:

Channel Status Application (5.2.2)

Yes, with restriction

Byte3 (sampling freq and clock accuracy)

b2829:

IEC60958-3

H/W auto set according to register setting

Channel Status Application (5.2.2)

b3235 :

24-bit original output sample is truncated

Byte4 (word length, original sampling

Yes, partially

to the specified word length.

rate, Byte0, b1, 6, 7 = 0)

b3639 :

Fixed to all zero (not indicated)

Specifying categories other than 0101010L (Digital

Category Code Groups (5.3.2)

Yes, with restriction

Sound Processor), especially those require non-zero

user data is not recommended.

User Data (6)

All zero

Clock accuracy indication is register settable.

Timing accuracy (7.2.1)

Yes

Expected to set level I (50 ppm) for master mode

(XTAL source) or level II (1000 ppm) for slave mode.

Standard output buffer. Needs external SPDIF driver

Line driver characteristics (7.3.2)

(ex.: optical driver)

(1)

Other sections of the specification not mentioned here are either considered irrelevant or covered elsewhere. IEC60958-4 is specific for

professional applications and thus, irrelevant.

The TAS3218 is has 10 analog stereo inputs that are multiplexed to one analog to digital converter (ADC).

Additionally, the TAS3218 has one line output that can source any of the 10 analog stereo inputs.

The TAS3218 has three stereo digital to analog converters (DAC). The outputs of of DAC3 are designed to be

used as a 24 mW headphone amplifier or line driver. The other two DAC outputs are configured as stereo line

drivers.

Both the ADC and DAC blocks can be placed in power down when not used.

Figure 16 shows a block diagram of the Analog interface.

The TAS3218 has a analog 10:1 input multiplexer and a 11:1 output multiplexer. These can accept analog stereo

inputs up to 1 Vrms. The outputs of the multiplexers are the stereo ADC and the line output.

The ADC supports a sampling rate of 48 kHz as a Clock Master Mode. In Clock Slave Mode, 32, 44.1, and 48

kHz sampling frequencies are supported, based upon the master clock frequency.

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