L6756D datasheet(22/36 Pages) STMICROELECTRONICS

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Output voltage positioning

L6756D

22/36

5.3

Output voltage load-line definition

L6756D is able to introduce a dependence of the output voltage on the load current

recovering part of the drop due to the output capacitor ESR in the load transient. Introducing

a dependence of the output voltage on the load current, a static error, proportional to the

output current, causes the output voltage to vary according to the sensed current.

Figure 7 shows the current sense circuit used to implement the load-line. The current

flowing across the inductor(s) is read through the R - C filter across CSx and CSxN pins. RG

programs a transconductance gain and generates a current ICSx proportional to the current

of the phase x. The sum of the ICSx current is then sourced by the VFB pin (IDROOP). RFB

gives the final gain to program the desired load-line slope (Figure 6).

Time constant matching between the inductor (L / DCR) and the current reading filter (RC)

is required to implement a real equivalent output impedance of the system so avoiding over

and/or under shoot of the output voltage as a consequence of a load transient. The output

characteristic vs. load current is then given by (Offset disabled):

Where RLL is the resulting load-line resistance implemented by the controller. The whole

power supply can be then represented by a “real” voltage generator with an equivalent

output resistance RLL and a voltage value of VID.

RFB resistor can be then designed according to the RLL specifications as follow:

Note:

Load-Line (DROOP) implementation is optional, in case it is not desired, the resulting

current information available on VDRP may be employed for other purposes, such as an

additional Load Indicator (LI2). In this case, simply connect a resistor RLI2 to SGND: the

resulting voltage drop across RLI2 will be proportional to the delivered current according to

the following relationship:

In case no additional information about the delivered current is requested, the VDRP pin can

be shorted to SGND.

5.4

Output voltage offset

The current (IOS) sunk from the VSEN pin allows programming a positive offset (VOS) for the

output voltage by connecting a resistor ROS to VOUT in series to the FB loop. The sunk cur-

rent generates a voltage drop according to the connected ROS. Output voltage is then pro-

grammed as follow:

Caution:

Offset resistor impacts the voltage positioning! It need to be considered in series to RFB.

Note:

Offset implementation is optional: in case it is not desired, simply consider using ROS = 0 Ω.

OUT

VID

DROOP

⋅

–

VID

DCR

------------- I

OUT

⋅⋅

–

VID

OUT

⋅

–

DCR

-------------

⋅

LI2

DCR

------------- I

OUT

⋅⋅

CORE

VID

() I

DROOP

⋅

–

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